add new option CS_OPT_MEM for cs_option(): this enable user-defined d…

…ynamic memory management. idea proposed by Pancake

MCInst.c

@@ -30,7 +30,7 @@ void MCInst_insert(MCInst *inst, int index, MCOperand *Op)
 	inst->Operands[index] = *Op;
 	inst->size++;
 
-	free(Op);
+	my_free(Op);
 }
 
 void MCInst_setOpcode(MCInst *inst, unsigned Op)
@@ -71,7 +71,7 @@ int MCInst_addOperand(MCInst *inst, MCOperand *Op)
 		return -1;
 
 	inst->Operands[inst->size] = *Op;
-	free(Op);
+	my_free(Op);
 
 	inst->size++;
 
@@ -152,7 +152,7 @@ void MCOperand_setFPImm(MCOperand *op, double Val)
 
 MCOperand *MCOperand_CreateReg(unsigned Reg)
 {
-	MCOperand *op = malloc(sizeof(*op)); 
+	MCOperand *op = my_malloc(sizeof(*op));
 
 	op->Kind = kRegister;
 	op->RegVal = Reg;
@@ -162,7 +162,7 @@ MCOperand *MCOperand_CreateReg(unsigned Reg)
 
 MCOperand *MCOperand_CreateImm(int64_t Val)
 {
-	MCOperand *op = malloc(sizeof(*op)); 
+	MCOperand *op = my_malloc(sizeof(*op));
 
 	op->Kind = kImmediate;
 	op->ImmVal = Val;
@@ -172,7 +172,7 @@ MCOperand *MCOperand_CreateImm(int64_t Val)
 
 MCOperand *MCOperand_CreateFPImm(double Val)
 {
-	MCOperand *op = malloc(sizeof(*op)); 
+	MCOperand *op = my_malloc(sizeof(*op));
 
 	op->Kind = kFPImmediate;
 	op->FPImmVal = Val;

arch/AArch64/AArch64BaseInfo.c

@@ -44,7 +44,7 @@ static bool compare_lower_str(char *s1, char *s2)
 		*c = tolower((int) *c);
 
 	bool res = (strcmp(s1, lower) == 0);
-	free(lower);
+	my_free(lower);
 
 	return res;
 }
@@ -615,10 +615,10 @@ void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *re
 	int dummy = sprintf(result, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
 	(void)dummy;
 
-	free(Op1S);
-	free(CRnS);
-	free(CRmS);
-	free(Op2S);
+	my_free(Op1S);
+	my_free(CRnS);
+	my_free(CRmS);
+	my_free(Op2S);
 }
 
 static NamedImmMapper_Mapping TLBIPairs[] = {

arch/AArch64/AArch64GenAsmWriter.inc

@@ -11759,7 +11759,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS, void *info)
   	  }
   }
 
-  free(tmp);
+  my_free(tmp);
 
   return true;
 }

arch/AArch64/AArch64InstPrinter.c

@@ -572,7 +572,7 @@ static void printVPRRegister(MCInst *MI, unsigned OpNo, SStream *O)
 	char *Name = strdup(getRegisterName(Reg));
 	Name[0] = 'v';
 	SStream_concat(O, "%s", Name);
-	free(Name);
+	my_free(Name);
 	if (MI->csh->detail) {
 		MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_REG;
 		MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].reg = Reg;
@@ -787,13 +787,13 @@ static void printVectorList(MCInst *MI, unsigned OpNum,
 			SStream_concat(O, "%s%s", Name, LayoutStr);
 			if (I != Count - 1)
 				SStream_concat(O, ", ");
-			free(Name);
+			my_free(Name);
 		}
 	} else { // Print the register directly when NumVecs is 1.
 		char *Name = strdup(getRegisterName(Reg));
 		Name[0] = 'v';
 		SStream_concat(O, "%s%s", Name, LayoutStr);
-		free(Name);
+		my_free(Name);
 	}
 	SStream_concat(O, "}");
 }
@@ -823,7 +823,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 		unsigned int id = AArch64_map_insn(mnem);
 		MCInst_setOpcode(MI, AArch64_get_insn_id2(id));
 		MCInst_setOpcodePub(MI, id);
-		free(mnem);
+		my_free(mnem);
 	} else
 		AArch64InstPrinter_printInstruction(MI, O, Info);
 }

arch/AArch64/mapping.c

@@ -3530,7 +3530,7 @@ arm64_reg AArch64_map_insn(const char *name)
 
 void AArch64_free_cache(void)
 {
-	free(insn_cache);
+	my_free(insn_cache);
 
 	insn_cache = NULL;
 }

arch/AArch64/module.c

@@ -2,6 +2,7 @@
 /* By Dang Hoang Vu <[email protected]> 2013 */
 
 #include "../../cs_priv.h"
+#include "../../utils.h"
 #include "../../MCRegisterInfo.h"
 #include "AArch64Disassembler.h"
 #include "AArch64InstPrinter.h"
@@ -10,7 +11,7 @@
 
 static cs_err init(cs_struct *ud)
 {
-	MCRegisterInfo *mri = malloc(sizeof(*mri));
+	MCRegisterInfo *mri = my_malloc(sizeof(*mri));
 
 	AArch64_init(mri);
 	ud->printer = AArch64_printInst;

arch/ARM/ARMGenAsmWriter.inc

@@ -8714,7 +8714,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS, void *info)
   	  }
   }
 
-  free(tmp);
+  my_free(tmp);
 
   return true;
 }

arch/ARM/ARMInstPrinter.c

@@ -520,7 +520,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
 					NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
 								MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
 					MCInst_addOperand2(&NewMI, NewReg);
-					free(NewReg);
+					my_free(NewReg);
 
 					// Copy the rest operands into NewMI.
 					unsigned i;

arch/ARM/mapping.c

@@ -2804,7 +2804,7 @@ bool ARM_rel_branch(unsigned int id)
 
 void ARM_free_cache(void)
 {
-	free(insn_cache);
+	my_free(insn_cache);
 
 	insn_cache = NULL;
 }

arch/ARM/module.c

@@ -10,7 +10,7 @@
 
 static cs_err init(cs_struct *ud)
 {
-	MCRegisterInfo *mri = malloc(sizeof(*mri));
+	MCRegisterInfo *mri = my_malloc(sizeof(*mri));
 
 	ARM_init(mri);
 

arch/Mips/MipsGenAsmWriter.inc

@@ -4470,7 +4470,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS, void *info)
       }
   }
 
-  free(tmp);
+  my_free(tmp);
 
   return true;
 }

arch/Mips/MipsInstPrinter.c

@@ -175,7 +175,7 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info)
 		unsigned id = Mips_map_insn(mnem);
 		MCInst_setOpcode(MI, Mips_get_insn_id2(id));
 		MCInst_setOpcodePub(MI, id);
-		free(mnem);
+		my_free(mnem);
 	}
 
 	switch (MCInst_getOpcode(MI)) {

arch/Mips/mapping.c

@@ -2037,7 +2037,7 @@ mips_reg Mips_map_register(unsigned int r)
 
 void Mips_free_cache(void)
 {
-	free(insn_cache);
+	my_free(insn_cache);
 
 	insn_cache = NULL;
 }

arch/Mips/module.c

@@ -2,6 +2,7 @@
 /* By Dang Hoang Vu <[email protected]> 2013 */
 
 #include "../../cs_priv.h"
+#include "../../utils.h"
 #include "../../MCRegisterInfo.h"
 #include "MipsDisassembler.h"
 #include "MipsInstPrinter.h"
@@ -10,7 +11,7 @@
 
 static cs_err init(cs_struct *ud)
 {
-	MCRegisterInfo *mri = malloc(sizeof(*mri));
+	MCRegisterInfo *mri = my_malloc(sizeof(*mri));
 
 	Mips_init(mri);
 	ud->printer = Mips_printInst;

arch/PowerPC/PPCGenAsmWriter.inc

@@ -3479,7 +3479,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS, void *info)
   	  }
   }
 
-  free(tmp);
+  my_free(tmp);
 
   return true;
 }

arch/PowerPC/mapping.c

@@ -1519,7 +1519,7 @@ ppc_reg PPC_map_register(unsigned int r)
 
 void PPC_free_cache(void)
 {
-	free(insn_cache);
+	my_free(insn_cache);
 
 	insn_cache = NULL;
 }

arch/PowerPC/module.c

@@ -2,6 +2,7 @@
 /* By Nguyen Anh Quynh <[email protected]>, 2013 */
 
 #include "../../cs_priv.h"
+#include "../../utils.h"
 #include "../../MCRegisterInfo.h"
 #include "PPCDisassembler.h"
 #include "PPCInstPrinter.h"
@@ -10,7 +11,7 @@
 
 static cs_err init(cs_struct *ud)
 {
-	MCRegisterInfo *mri = malloc(sizeof(*mri));
+	MCRegisterInfo *mri = my_malloc(sizeof(*mri));
 
 	PPC_init(mri);
 	ud->printer = PPC_printInst;

arch/X86/X86ATTInstPrinter.c

@@ -454,7 +454,7 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
 			*tab = '\0';
 		// reflect the new insn name (alias) in the opcode
 		MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem)));
-		free(mnem);
+		my_free(mnem);
 	} else
 	   printInstruction(MI, OS);
 

arch/X86/X86GenAsmWriter.inc

@@ -13397,7 +13397,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS)
       }
   }
 
-  free(tmp);
+  my_free(tmp);
 
   return true;
 }

arch/X86/X86GenAsmWriter1.inc

@@ -12886,7 +12886,7 @@ static bool printAliasInstr(MCInst *MI, SStream *OS)
       }
   }
 
-  free(tmp);
+  my_free(tmp);
 
   return true;
 }

arch/X86/X86IntelInstPrinter.c

@@ -230,7 +230,7 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
 			*tab = '\0';
 		// reflect the new insn name (alias) in the opcode
 		MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem)));
-		free(mnem);
+		my_free(mnem);
 	} else
 		printInstruction(MI, O);
 

arch/X86/mapping.c

@@ -6642,6 +6642,6 @@ unsigned int X86_get_insn_id2(unsigned int id)
 
 void X86_free_cache(void)
 {
-	free(insn_cache);
+	my_free(insn_cache);
 	insn_cache = NULL;
 }