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Commits on Aug 21, 2016

• Fix compile error in vsim

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• Also integrate SPI tb and cleanup spi pkg. Almost ready to use the spi

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• Move separate tb.sv files (except spi one) to global tb.sv and use TEST

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• Add clean target to all makefiles and fix typo

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  committed
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• Try to fix board issues ZedBoard vs ZYBO

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  committed
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Commits on Aug 7, 2016

• Make I2C eeprom model work

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  committed
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Commits on Jul 31, 2016

• Have to change to ttyPS1 for zybo.. this breaks compatibility with

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• Update devicetree and spiloader

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• Fix devicetree and block diagram for zybo

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  committed
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Commits on Jul 29, 2016

• Added a simple i2c model for simulation. Needs integration now

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Commits on Jul 21, 2016

• Same same but based on libc implementation

  

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  authored and

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  committed
  07bced5

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• Try adding ctors to crt0 for cxx and link cxx libraries necessary for this

  

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Commits on Jul 19, 2016

• Linux boots now. Unclear if usb + ethernet works though

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  committed
  c26bfdd

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• Same same but based on libc implementation

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  committed
  883dd1c

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• Try adding ctors to crt0 for cxx and link cxx libraries necessary for this

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  committed
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Commits on Jul 10, 2016

• Working on ZYBO support for Arduino

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Commits on Jun 18, 2016

• Clarified timer interrupts after feedback from Mohr

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Commits on May 17, 2016

• Modify shuffle pack to test more cases

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  committed
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• Align testCnt with new meaning of ff1, fl1 and clb

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  committed
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Commits on May 12, 2016

• Add dbg resume signal to core, bound to 0 because not used in single-core system

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Commits on May 11, 2016

• Fix debug test for RVC

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• add the rest of the performance counters to the print

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• Switch compiler for CI

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• Properly exit on illegal instruction

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  committed
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• Also add testEvents to riscv testset

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• Actually also wake up during interrupt test

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• Check interrupts during sleep periods

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• Return correctly for error reporting

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  committed
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• Export JTAG pins on FPGA to be able to attach an external debugger

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• Add event lines description

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Commits on May 10, 2016

• Target Xpulpv2 now

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• Revert part of last commit

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• Check read and write when FIFO gets empty

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• Change interrupt handler addresses

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• Add read/write to SPI flash to testSPIMaster

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  committed
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