config: use optional override offsets

rajatbh21 · Jun 17, 2020 · 77532ca · 77532ca
1 parent ece6b14
commit 77532ca
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Showing 3 changed files with 46 additions and 32 deletions.
diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala
@@ -34,30 +34,38 @@ class GroundTestBaseConfig extends Config(
   })
 )
 
-class WithTraceGen(n: Int = 2, idOffset: Int = 0)(
+class WithTraceGen(
+  n: Int = 2,
+  overrideIdOffset: Option[Int] = None,
+  overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
   nReqs: Int = 8192
 ) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => params.zipWithIndex.map { case (dcp, i) =>
-    TraceGenTileAttachParams(
-      tileParams = TraceGenParams(
-        hartId = i + idOffset,
-        dcache = Some(dcp),
-        wordBits = site(XLen),
-        addrBits = 32,
-        addrBag = {
-          val nSets = dcp.nSets
-          val nWays = dcp.nWays
-          val blockOffset = site(SystemBusKey).blockOffset
-          val nBeats = site(SystemBusKey).blockBeats
-          List.tabulate(nWays) { i =>
-            Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
-          }.flatten
-        },
-        maxRequests = nReqs,
-        memStart = site(ExtMem).get.master.base,
-        numGens = params.size),
-      crossingParams = RocketCrossingParams()
-    )
-  } ++ up(TilesLocated(InSubsystem), site)
+  case TilesLocated(InSubsystem) => {
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = overrideIdOffset.getOrElse(prev.size)
+    val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
+    params.zipWithIndex.map { case (dcp, i) =>
+      TraceGenTileAttachParams(
+        tileParams = TraceGenParams(
+          hartId = i + idOffset,
+          dcache = Some(dcp),
+          wordBits = site(XLen),
+          addrBits = 32,
+          addrBag = {
+            val nSets = dcp.nSets
+            val nWays = dcp.nWays
+            val blockOffset = site(SystemBusKey).blockOffset
+            val nBeats = site(SystemBusKey).blockBeats
+            List.tabulate(nWays) { i =>
+              Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
+            }.flatten
+          },
+          maxRequests = nReqs,
+          memStart = memOffset,
+          numGens = params.size),
+        crossingParams = RocketCrossingParams()
+      )
+    } ++ prev
+  }
 })
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -77,8 +77,10 @@ class WithCoherentBusTopology extends Config((site, here, up) => {
       l2 = site(BankedL2Key)))
 })
 
-class WithNBigCores(n: Int, idOffset: Int = 0) extends Config((site, here, up) => {
+class WithNBigCores(n: Int, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
   case RocketTilesKey => {
+    val prev = up(RocketTilesKey, site)
+    val idOffset = overrideIdOffset.getOrElse(prev.size)
     val big = RocketTileParams(
       core   = RocketCoreParams(mulDiv = Some(MulDivParams(
         mulUnroll = 8,
@@ -91,12 +93,14 @@ class WithNBigCores(n: Int, idOffset: Int = 0) extends Config((site, here, up) =
       icache = Some(ICacheParams(
         rowBits = site(SystemBusKey).beatBits,
         blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => big.copy(hartId = i + idOffset)) ++ up(RocketTilesKey, site)
+    List.tabulate(n)(i => big.copy(hartId = i + idOffset)) ++ prev
   }
 })
 
-class WithNMedCores(n: Int, idOffset: Int = 0) extends Config((site, here, up) => {
+class WithNMedCores(n: Int, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
   case RocketTilesKey => {
+    val prev = up(RocketTilesKey, site)
+    val idOffset = overrideIdOffset.getOrElse(prev.size)
     val med = RocketTileParams(
       core = RocketCoreParams(fpu = None),
       btb = None,
@@ -113,12 +117,14 @@ class WithNMedCores(n: Int, idOffset: Int = 0) extends Config((site, here, up) =
         nWays = 1,
         nTLBEntries = 4,
         blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => med.copy(hartId = i + idOffset)) ++ up(RocketTilesKey, site)
+    List.tabulate(n)(i => med.copy(hartId = i + idOffset)) ++ prev
   }
 })
 
-class WithNSmallCores(n: Int, idOffset: Int = 0) extends Config((site, here, up) => {
+class WithNSmallCores(n: Int, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
   case RocketTilesKey => {
+    val prev = up(RocketTilesKey, site)
+    val idOffset = overrideIdOffset.getOrElse(prev.size)
     val small = RocketTileParams(
       core = RocketCoreParams(useVM = false, fpu = None),
       btb = None,
@@ -135,7 +141,7 @@ class WithNSmallCores(n: Int, idOffset: Int = 0) extends Config((site, here, up)
         nWays = 1,
         nTLBEntries = 4,
         blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => small.copy(hartId = i + idOffset)) ++ up(RocketTilesKey, site)
+    List.tabulate(n)(i => small.copy(hartId = i + idOffset)) ++ prev
   }
 })
 

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
@@ -40,9 +40,9 @@ class DualChannelDualBankConfig extends Config(
 class RoccExampleConfig extends Config(new WithRoccExample ++ new DefaultConfig)
 
 class HeterogeneousTileExampleConfig extends Config(
-  new WithTraceGen (n = 2, idOffset = 3)() ++
-  new WithNBigCores(n = 1, idOffset = 2) ++
-  new WithNMedCores(n = 1, idOffset = 1) ++
+  new WithTraceGen (n = 2, overrideMemOffset = Some(0x90000000L))() ++
+  new WithNBigCores(n = 1) ++
+  new WithNMedCores(n = 1) ++
   new WithNSmallCores(n = 1) ++
   new WithCoherentBusTopology ++
   new BaseConfig