[mips] Remove codegen support from some 16 bit instructions

These instructions conflict with their full length variants
for the purposes of FastISel as they cannot be distingushed
based on the number and type of operands and predicates.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D41285


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325341 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MicroMips32r6InstrInfo.td

@@ -1068,19 +1068,14 @@ class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
       MMR6Arch<"addu16"> {
   int AddedComplexity = 1;
 }
-class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
-      MMR6Arch<"and16"> {
-  int AddedComplexity = 1;
-}
+class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
+      MMR6Arch<"and16">;
 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
   int AddedComplexity = 1;
 }
-class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
-      MMR6Arch<"or16"> {
-  int AddedComplexity = 1;
-}
+class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
       MMR6Arch<"sll16">;
 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
@@ -1098,10 +1093,8 @@ class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
       MMR6Arch<"subu16">, MicroMipsR6Inst16 {
   int AddedComplexity = 1;
 }
-class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-      MMR6Arch<"xor16"> {
-  int AddedComplexity = 1;
-}
+class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
+      MMR6Arch<"xor16">;
 
 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);

test/CodeGen/Mips/llvm-ir/and.ll

@@ -72,8 +72,7 @@ define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
 ;
 ; MM32R6-LABEL: and_i1:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    and16 $4, $5
-; MM32R6-NEXT:    move $2, $4
+; MM32R6-NEXT:    and $2, $4, $5
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %r = and i1 %a, %b
@@ -122,8 +121,7 @@ define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
 ;
 ; MM32R6-LABEL: and_i8:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    and16 $4, $5
-; MM32R6-NEXT:    move $2, $4
+; MM32R6-NEXT:    and $2, $4, $5
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %r = and i8 %a, %b
@@ -172,8 +170,7 @@ define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
 ;
 ; MM32R6-LABEL: and_i16:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    and16 $4, $5
-; MM32R6-NEXT:    move $2, $4
+; MM32R6-NEXT:    and $2, $4, $5
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %r = and i16 %a, %b
@@ -222,8 +219,7 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 ;
 ; MM32R6-LABEL: and_i32:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    and16 $4, $5
-; MM32R6-NEXT:    move $2, $4
+; MM32R6-NEXT:    and $2, $4, $5
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %r = and i32 %a, %b
@@ -274,10 +270,8 @@ define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
 ;
 ; MM32R6-LABEL: and_i64:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    and16 $4, $6
-; MM32R6-NEXT:    and16 $5, $7
-; MM32R6-NEXT:    move $2, $4
-; MM32R6-NEXT:    move $3, $5
+; MM32R6-NEXT:    and $2, $4, $6
+; MM32R6-NEXT:    and $3, $5, $7
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %r = and i64 %a, %b
@@ -353,14 +347,14 @@ define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
 ;
 ; MM32R6-LABEL: and_i128:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    lw $3, 20($sp)
+; MM32R6-NEXT:    lw $1, 20($sp)
 ; MM32R6-NEXT:    lw $2, 16($sp)
-; MM32R6-NEXT:    and16 $2, $4
-; MM32R6-NEXT:    and16 $3, $5
-; MM32R6-NEXT:    lw $4, 24($sp)
-; MM32R6-NEXT:    and16 $4, $6
-; MM32R6-NEXT:    lw $5, 28($sp)
-; MM32R6-NEXT:    and16 $5, $7
+; MM32R6-NEXT:    and $2, $4, $2
+; MM32R6-NEXT:    and $3, $5, $1
+; MM32R6-NEXT:    lw $1, 24($sp)
+; MM32R6-NEXT:    and $4, $6, $1
+; MM32R6-NEXT:    lw $1, 28($sp)
+; MM32R6-NEXT:    and $5, $7, $1
 ; MM32R6-NEXT:    jrc $ra
 entry:
   %r = and i128 %a, %b
@@ -1381,8 +1375,8 @@ define signext i16 @and_i16_32768(i16 signext %b) {
 ;
 ; MM32R6-LABEL: and_i16_32768:
 ; MM32R6:       # %bb.0: # %entry
-; MM32R6-NEXT:    addiu $2, $zero, -32768
-; MM32R6-NEXT:    and16 $2, $4
+; MM32R6-NEXT:    addiu $1, $zero, -32768
+; MM32R6-NEXT:    and $2, $4, $1
 ; MM32R6-NEXT:    jrc $ra
 entry:
 

test/CodeGen/Mips/llvm-ir/ashr.ll

@@ -388,7 +388,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
 ; MMR6-NEXT:    not16 $6, $7
 ; MMR6-NEXT:    sll16 $4, $4, 1
 ; MMR6-NEXT:    sllv $4, $4, $6
-; MMR6-NEXT:    or16 $4, $5
+; MMR6-NEXT:    or $4, $4, $5
 ; MMR6-NEXT:    seleqz $4, $4, $3
 ; MMR6-NEXT:    selnez $1, $1, $3
 ; MMR6-NEXT:    or $3, $1, $4
@@ -877,104 +877,89 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
 ;
 ; MMR6-LABEL: ashr_i128:
 ; MMR6:       # %bb.0: # %entry
-; MMR6-NEXT:    addiu $sp, $sp, -40
-; MMR6-NEXT:    .cfi_def_cfa_offset 40
-; MMR6-NEXT:    sw $17, 36($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    sw $16, 32($sp) # 4-byte Folded Spill
+; MMR6-NEXT:    addiu $sp, $sp, -16
+; MMR6-NEXT:    .cfi_def_cfa_offset 16
+; MMR6-NEXT:    sw $17, 12($sp) # 4-byte Folded Spill
+; MMR6-NEXT:    sw $16, 8($sp) # 4-byte Folded Spill
 ; MMR6-NEXT:    .cfi_offset 17, -4
 ; MMR6-NEXT:    .cfi_offset 16, -8
 ; MMR6-NEXT:    move $1, $7
-; MMR6-NEXT:    sw $6, 28($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    move $6, $5
-; MMR6-NEXT:    sw $4, 12($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    lw $3, 68($sp)
+; MMR6-NEXT:    lw $3, 44($sp)
 ; MMR6-NEXT:    li16 $2, 64
 ; MMR6-NEXT:    subu16 $7, $2, $3
 ; MMR6-NEXT:    sllv $8, $5, $7
-; MMR6-NEXT:    andi16 $5, $7, 32
-; MMR6-NEXT:    selnez $9, $8, $5
-; MMR6-NEXT:    sllv $16, $4, $7
+; MMR6-NEXT:    andi16 $2, $7, 32
+; MMR6-NEXT:    selnez $9, $8, $2
+; MMR6-NEXT:    sllv $10, $4, $7
 ; MMR6-NEXT:    not16 $7, $7
-; MMR6-NEXT:    srl16 $17, $6, 1
-; MMR6-NEXT:    sw $6, 20($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    srlv $7, $17, $7
-; MMR6-NEXT:    or16 $7, $16
-; MMR6-NEXT:    seleqz $7, $7, $5
+; MMR6-NEXT:    srl16 $16, $5, 1
+; MMR6-NEXT:    srlv $7, $16, $7
+; MMR6-NEXT:    or $7, $10, $7
+; MMR6-NEXT:    seleqz $7, $7, $2
 ; MMR6-NEXT:    or $7, $9, $7
-; MMR6-NEXT:    srlv $17, $1, $3
-; MMR6-NEXT:    not16 $2, $3
-; MMR6-NEXT:    sw $2, 24($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    lw $4, 28($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    sll16 $16, $4, 1
-; MMR6-NEXT:    sllv $16, $16, $2
-; MMR6-NEXT:    or16 $16, $17
+; MMR6-NEXT:    srlv $9, $1, $3
+; MMR6-NEXT:    not16 $16, $3
+; MMR6-NEXT:    sw $16, 4($sp) # 4-byte Folded Spill
+; MMR6-NEXT:    sll16 $17, $6, 1
+; MMR6-NEXT:    sllv $10, $17, $16
+; MMR6-NEXT:    or $9, $10, $9
 ; MMR6-NEXT:    andi16 $17, $3, 32
-; MMR6-NEXT:    seleqz $9, $16, $17
-; MMR6-NEXT:    srlv $10, $4, $3
+; MMR6-NEXT:    seleqz $9, $9, $17
+; MMR6-NEXT:    srlv $10, $6, $3
 ; MMR6-NEXT:    selnez $11, $10, $17
-; MMR6-NEXT:    seleqz $16, $10, $17
-; MMR6-NEXT:    or16 $16, $7
-; MMR6-NEXT:    seleqz $2, $8, $5
-; MMR6-NEXT:    sw $2, 8($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    or $7, $11, $9
+; MMR6-NEXT:    seleqz $10, $10, $17
+; MMR6-NEXT:    or $10, $10, $7
+; MMR6-NEXT:    seleqz $12, $8, $2
+; MMR6-NEXT:    or $8, $11, $9
 ; MMR6-NEXT:    addiu $2, $3, -64
-; MMR6-NEXT:    srlv $4, $6, $2
-; MMR6-NEXT:    sw $4, 4($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    lw $5, 12($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    sll16 $4, $5, 1
-; MMR6-NEXT:    sw $4, 16($sp) # 4-byte Folded Spill
-; MMR6-NEXT:    not16 $6, $2
-; MMR6-NEXT:    sllv $6, $4, $6
-; MMR6-NEXT:    sltiu $8, $3, 64
-; MMR6-NEXT:    move $4, $7
-; MMR6-NEXT:    lw $7, 8($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    or16 $4, $7
-; MMR6-NEXT:    selnez $9, $16, $8
-; MMR6-NEXT:    lw $7, 4($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    or16 $6, $7
-; MMR6-NEXT:    srav $7, $5, $2
+; MMR6-NEXT:    srlv $9, $5, $2
+; MMR6-NEXT:    sll16 $7, $4, 1
+; MMR6-NEXT:    not16 $16, $2
+; MMR6-NEXT:    sllv $11, $7, $16
+; MMR6-NEXT:    sltiu $13, $3, 64
+; MMR6-NEXT:    or $8, $8, $12
+; MMR6-NEXT:    selnez $10, $10, $13
+; MMR6-NEXT:    or $9, $11, $9
+; MMR6-NEXT:    srav $11, $4, $2
 ; MMR6-NEXT:    andi16 $2, $2, 32
-; MMR6-NEXT:    seleqz $10, $7, $2
-; MMR6-NEXT:    sra $11, $5, 31
-; MMR6-NEXT:    selnez $12, $11, $2
-; MMR6-NEXT:    seleqz $6, $6, $2
-; MMR6-NEXT:    or $10, $12, $10
-; MMR6-NEXT:    seleqz $10, $10, $8
-; MMR6-NEXT:    selnez $2, $7, $2
-; MMR6-NEXT:    seleqz $7, $11, $8
-; MMR6-NEXT:    or $9, $9, $10
-; MMR6-NEXT:    selnez $9, $9, $3
-; MMR6-NEXT:    selnez $4, $4, $8
-; MMR6-NEXT:    or $2, $2, $6
-; MMR6-NEXT:    srav $5, $5, $3
-; MMR6-NEXT:    seleqz $6, $5, $17
-; MMR6-NEXT:    selnez $10, $11, $17
-; MMR6-NEXT:    or $6, $10, $6
-; MMR6-NEXT:    selnez $6, $6, $8
-; MMR6-NEXT:    seleqz $2, $2, $8
-; MMR6-NEXT:    lw $16, 28($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    seleqz $10, $16, $3
+; MMR6-NEXT:    seleqz $12, $11, $2
+; MMR6-NEXT:    sra $14, $4, 31
+; MMR6-NEXT:    selnez $15, $14, $2
+; MMR6-NEXT:    seleqz $9, $9, $2
+; MMR6-NEXT:    or $12, $15, $12
+; MMR6-NEXT:    seleqz $12, $12, $13
+; MMR6-NEXT:    selnez $2, $11, $2
+; MMR6-NEXT:    seleqz $11, $14, $13
+; MMR6-NEXT:    or $10, $10, $12
+; MMR6-NEXT:    selnez $10, $10, $3
+; MMR6-NEXT:    selnez $8, $8, $13
+; MMR6-NEXT:    or $2, $2, $9
+; MMR6-NEXT:    srav $9, $4, $3
+; MMR6-NEXT:    seleqz $4, $9, $17
+; MMR6-NEXT:    selnez $12, $14, $17
+; MMR6-NEXT:    or $4, $12, $4
+; MMR6-NEXT:    selnez $12, $4, $13
+; MMR6-NEXT:    seleqz $2, $2, $13
+; MMR6-NEXT:    seleqz $4, $6, $3
 ; MMR6-NEXT:    seleqz $1, $1, $3
-; MMR6-NEXT:    or $2, $4, $2
+; MMR6-NEXT:    or $2, $8, $2
 ; MMR6-NEXT:    selnez $2, $2, $3
 ; MMR6-NEXT:    or $1, $1, $2
-; MMR6-NEXT:    or $4, $10, $9
-; MMR6-NEXT:    or $2, $6, $7
-; MMR6-NEXT:    lw $6, 20($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    srlv $3, $6, $3
-; MMR6-NEXT:    lw $6, 24($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    lw $16, 16($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    sllv $6, $16, $6
-; MMR6-NEXT:    or16 $6, $3
-; MMR6-NEXT:    seleqz $3, $6, $17
-; MMR6-NEXT:    selnez $5, $5, $17
+; MMR6-NEXT:    or $4, $4, $10
+; MMR6-NEXT:    or $2, $12, $11
+; MMR6-NEXT:    srlv $3, $5, $3
+; MMR6-NEXT:    lw $5, 4($sp) # 4-byte Folded Reload
+; MMR6-NEXT:    sllv $5, $7, $5
 ; MMR6-NEXT:    or $3, $5, $3
-; MMR6-NEXT:    selnez $3, $3, $8
-; MMR6-NEXT:    or $3, $3, $7
+; MMR6-NEXT:    seleqz $3, $3, $17
+; MMR6-NEXT:    selnez $5, $9, $17
+; MMR6-NEXT:    or $3, $5, $3
+; MMR6-NEXT:    selnez $3, $3, $13
+; MMR6-NEXT:    or $3, $3, $11
 ; MMR6-NEXT:    move $5, $1
-; MMR6-NEXT:    lw $16, 32($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    lw $17, 36($sp) # 4-byte Folded Reload
-; MMR6-NEXT:    addiu $sp, $sp, 40
+; MMR6-NEXT:    lw $16, 8($sp) # 4-byte Folded Reload
+; MMR6-NEXT:    lw $17, 12($sp) # 4-byte Folded Reload
+; MMR6-NEXT:    addiu $sp, $sp, 16
 ; MMR6-NEXT:    jrc $ra
 entry:
 ; o32 shouldn't use TImode helpers.