Computer Architecture 2 at Arizona State University - Under Yann Hang Lee

Collect some CS textbooks for learning.

A comprehensive roadmap for aspiring Embedded Systems Engineers, featuring a curated list of learning resources.

A curated list of awesome embedded programming.

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

A beautiful, simple, clean, and responsive Jekyll theme for academics

Matplotlib styles for scientific plotting

Official inference framework for 1-bit LLMs

It is just to share what my own learnings about Low Level Design. (LLD)

STM32 tutorial with STM32Cube and Keil MDK-ARM

A STM32 HAL library tutorial

This blog also contains interview questions related to Embedded Systems, Linux BSP, Linux Kernel, ARM Architecture, C programming etc

STM32Cube MCU Full Package for the STM32H7 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Dis…

Verilog HDL files

Crack your Embedded Interview

📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

Short notes I made for GATE CSE subjects during my gate preparation from 2018 to 2021.

LLM101n: Let's build a Storyteller

A curated list of all the open-source internships/Programs

Find here every 🎯 Open Source Programs | Internships | Competitions | Fellowships in a systematic way. Most imp. " Deadlines are mentioned for Registration" .

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

Implementing Different Adder Structures in Verilog

It's a basic computer designed using VERILOG on XILINX FPGA architecture.

CMPE 140 - Computer Architecture and Design

CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.

ES-203 Computer Organization & Architecture CNN on FPGA board

Hardware designs modelled with verilog

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum