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Tags: riscvarchive/riscv-binutils-gdb
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Support vector constraints for whole register load, store and move. For vl<nf>r.v and vs<nf>r.v Instructions, `rd` plus the `nf` value cannot exceed 31. But we just support single vector register moved for loads and stores, so don't need to do any contraints checking for them. As for vmv<nf>r.v, we only support the standard aligned vector register groups currently.
Merge pull request #182 from Nelson1225/rvv-0.8.x-nelson Update to 0.8-draft-20191004.