Verilog-Snippets

A host for small Verilog-Snippets brewed during Lab Sessions of Computer Architecture Course at BITS-Pilani.

• This repository will hold certain scratch-pad models of MIPS(Microprocessor without Interlocked Pipeline Stages) DataPath and Control Unit for different implementations.

• It may at later stages also contain certain parts related to Memory Segment.

Instructor-In-Charge: Sudeept Mohan

References :

1. Computer Organisation and Design by Petterson,Hennesy
2. Verilog HDL by Samir Palnitkar