Following files are included in this project:
CS203 Project Proposal : This file contains a doc file giving the idea of what the project is about.
Project Submission Intermediate : Contains the intermediate submission of the project which includes the Modules used, Inputs and Output ports.
CS203_project_design.v : this is a .v file which contains the verilog code of the design module of this project.
CS203_project_design.txt : .txt file which contains the verilog code of the design module of this project.
CS203_project_testbench.v : this is a .v file which contains the verilog code of the testbench of this project.
CS203_project_testbench.txt : .txt file which contains the verilog code of the testbench of this project.
Output.vcd : Output file generated after the testbench.