examples: Working UART for Versa SoC demo

Signed-off-by: David Shah <[email protected]>

examples/soc_versa5g/Makefile

@@ -7,14 +7,14 @@ firmware.bin: firmware.elf
 firmware.hex: firmware.bin
 	python3 makehex.py $^ 4096 > $@
 
-attosoc_tb.vvp: attosoc_tb.v attosoc.v picorv32.v
+attosoc_tb.vvp: attosoc_tb.v attosoc.v picorv32.v simpleuart.v
 	iverilog -s testbench -o $@ $^
 
 attosoc_sim: attosoc_tb.vvp firmware.hex
 	vvp -N $<
 
 attosoc.json: io_wrapper.v attosoc.v picorv32.v firmware.hex
-	yosys -p "synth_ecp5 -nomux -json $@ -top top" io_wrapper.v attosoc.v picorv32.v
+	yosys -p "synth_ecp5 -nomux -json $@ -top top" io_wrapper.v attosoc.v picorv32.v simpleuart.v
 
 attosoc_out.config: attosoc.json
 	nextpnr-ecp5 --json $< --basecfg ../../misc/basecfgs/empty_lfe5um5g-45f.config --textcfg $@ --45k

examples/soc_versa5g/attosoc.v

@@ -26,7 +26,9 @@
 
 module attosoc (
 	input clk,
-	output reg [7:0] led
+	output reg [7:0] led,
+	output uart_tx,
+	input uart_rx
 );
 
 	reg [5:0] reset_cnt = 0;
@@ -36,7 +38,7 @@ module attosoc (
 		reset_cnt <= reset_cnt + !resetn;
 	end
 
-	parameter integer MEM_WORDS = 4096;
+	parameter integer MEM_WORDS = 8192;
 	parameter [31:0] STACKADDR = 32'h 0000_0000 + (4*MEM_WORDS);       // end of memory
 	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000;       // start of memory
 
@@ -61,35 +63,47 @@ module attosoc (
 			if (mem_wstrb[1]) ram[mem_addr[23:2]][15:8] <= mem_wdata[15:8];
 			if (mem_wstrb[2]) ram[mem_addr[23:2]][23:16] <= mem_wdata[23:16];
 			if (mem_wstrb[3]) ram[mem_addr[23:2]][31:24] <= mem_wdata[31:24];
-			
+
 			ram_rdata <= ram[mem_addr[23:2]];
 			ram_ready <= 1'b1;
 		end
         end
 
 	wire iomem_valid;
-	wire iomem_ready;
+	reg iomem_ready;
 	wire [31:0] iomem_addr;
 	wire [31:0] iomem_wdata;
 	wire [3:0] iomem_wstrb;
 	wire [31:0] iomem_rdata;
 
 	assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
-	assign iomem_ready = 1'b1;
 	assign iomem_wstrb = mem_wstrb;
 	assign iomem_addr = mem_addr;
 	assign iomem_wdata = mem_wdata;
 
-	wire [31:0] spimemio_cfgreg_do;
+	wire        simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
+	wire [31:0] simpleuart_reg_div_do;
+
+	wire        simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
+	wire [31:0] simpleuart_reg_dat_do;
+	wire simpleuart_reg_dat_wait;
 
+	always @(posedge clk) begin
+		iomem_ready <= 1'b0;
+	  if (iomem_valid && iomem_wstrb[0] && mem_addr == 32'h 02000000) begin
+	    led <= iomem_wdata[7:0];
+			iomem_ready <= 1'b1;
+		end
+	end
 
-        always @(posedge clk)
-          if (iomem_valid && iomem_wstrb[0])
-            led <= iomem_wdata[7:0];
 
-	assign mem_ready = (iomem_valid && iomem_ready) || ram_ready;
+	assign mem_ready = (iomem_valid && iomem_ready) ||
+	                   simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait) ||
+										 ram_ready;
 
-	assign mem_rdata = ram_rdata;
+	assign mem_rdata = simpleuart_reg_div_sel ? simpleuart_reg_div_do :
+										 simpleuart_reg_dat_sel ? simpleuart_reg_dat_do :
+ 											ram_rdata;
 
 	picorv32 #(
 		.STACKADDR(STACKADDR),
@@ -113,7 +127,23 @@ module attosoc (
 		.mem_rdata   (mem_rdata  )
 	);
 
+	simpleuart simpleuart (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+
+		.ser_tx      (uart_tx     ),
+		.ser_rx      (uart_rx     ),
 
+		.reg_div_we  (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
+		.reg_div_di  (mem_wdata),
+		.reg_div_do  (simpleuart_reg_div_do),
+
+		.reg_dat_we  (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
+		.reg_dat_re  (simpleuart_reg_dat_sel && !mem_wstrb),
+		.reg_dat_di  (mem_wdata),
+		.reg_dat_do  (simpleuart_reg_dat_do),
+		.reg_dat_wait(simpleuart_reg_dat_wait)
+);
 
 endmodule
 

examples/soc_versa5g/attosoc_tb.v

@@ -9,8 +9,8 @@ module testbench();
 		$dumpvars(0, testbench);
 
 		repeat (10) begin
-			repeat (256) @(posedge clk);
-			$display("+256 cycles");
+			repeat (50000) @(posedge clk);
+			$display("+50000 cycles");
 		end
 		$finish;
 	end

examples/soc_versa5g/firmware.c

@@ -2,14 +2,32 @@
 
 #define LED (*(volatile uint32_t*)0x02000000)
 
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004)
+#define reg_uart_data (*(volatile uint32_t*)0x02000008)
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
+
 void delay() {
    for (volatile int i = 0; i < 50000; i++)
 	   ;
 }
 
 int main() {
+  	reg_uart_clkdiv = 509;
    while (1) {
 	LED = 0xFF;
+  print("hello world\n");
 	delay();
 	LED = 0x00;
 	delay();

examples/soc_versa5g/io_wrapper.v

@@ -1,12 +1,14 @@
 module top(
 	input clk_pin,
 	output [7:0] led_pin,
-        output clken_pin
+	output uart_tx_pin,
+	input uart_rx_pin,
+  output clken_pin
 );
 
 wire clk;
 wire [7:0] led;
-
+wire uart_rx, uart_tx;
 reg [4:0] divclk;
 
 always @(posedge clk)
@@ -33,13 +35,20 @@ TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(!led[6]));
 (* LOC="F16" *) (* IO_TYPE="LVCMOS25" *)
 TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(!led[7]));
 
+(* LOC="A11" *) (* IO_TYPE="LVCMOS33" *)
+TRELLIS_IO #(.DIR("OUTPUT")) utx_buf (.B(uart_tx_pin), .I(uart_tx));
+(* LOC="C11" *) (* IO_TYPE="LVCMOS33" *)
+TRELLIS_IO #(.DIR("INPUT")) urx_buf (.B(uart_rx_pin), .O(uart_rx));
+
 (* LOC="C12" *) (* IO_TYPE="LVCMOS33" *)
 TRELLIS_IO #(.DIR("OUTPUT")) clken_buf (.B(clken_pin), .I(1'b1));
 
 
 attosoc soc(
 	.clk(divclk[4]),
-	.led(led)
+	.led(led),
+	.uart_tx(uart_tx),
+	.uart_rx(uart_rx)
 );
 
 

examples/soc_versa5g/sections.lds

@@ -1,6 +1,6 @@
 MEMORY
 {
-    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x004000 /* 16 KB */
+    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x008000 /* 32 KB */
 }
 
 SECTIONS {