libtrellis: Expose name to row-column mapping in Pytrellis.

Signed-off-by: William D. Jones <[email protected]>
rroohhh · Nov 12, 2018 · aec0b25 · aec0b25
1 parent 47d3cb1
commit aec0b25
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Showing 3 changed files with 28 additions and 16 deletions.
diff --git a/libtrellis/include/Tile.hpp b/libtrellis/include/Tile.hpp
@@ -8,12 +8,9 @@
 #include <regex>
 #include <cassert>
 #include "CRAM.hpp"
-#include "Util.hpp"
 
 namespace Trellis {
-
-// Regex to extract row/column from a tile name
-static const regex tile_row_col_re(R"(R(\d+)C(\d+))");
+pair<int, int> get_row_col_pair_from_chipsize(string name, pair<int, int> chip_size, int bias);
 
 // Basic information about a site
 struct SiteInfo {
@@ -43,17 +40,10 @@ struct TileInfo {
     vector<SiteInfo> sites;
 
     inline pair<int, int> get_row_col() const {
-        smatch m;
-        bool match;
-
-        match = regex_search(name, m, tile_row_col_re);
-        if(match) {
-            auto row_col = make_pair(stoi(m.str(1)), stoi(m.str(2)));
-            assert(row_col <= make_pair(int(max_row), int(max_col)));
-            return row_col;
-        } else {
-            throw runtime_error(fmt("Could not extract position from " << name));
-        }
+        auto chip_size = make_pair(int(max_row), int(max_col));
+        auto row_col = get_row_col_pair_from_chipsize(name, chip_size, col_bias);
+        assert(row_col <= chip_size);
+        return row_col;
     };
 
     // Get the Lattice name

diff --git a/libtrellis/src/PyTrellis.cpp b/libtrellis/src/PyTrellis.cpp
@@ -81,7 +81,10 @@ BOOST_PYTHON_MODULE (pytrellis)
             .def_readonly("num_frames", &ChipInfo::num_frames)
             .def_readonly("bits_per_frame", &ChipInfo::bits_per_frame)
             .def_readonly("pad_bits_before_frame", &ChipInfo::pad_bits_before_frame)
-            .def_readonly("pad_bits_after_frame", &ChipInfo::pad_bits_after_frame);
+            .def_readonly("pad_bits_after_frame", &ChipInfo::pad_bits_after_frame)
+            .def_readonly("max_row", &ChipInfo::max_row)
+            .def_readonly("max_col", &ChipInfo::max_col)
+            .def_readonly("col_bias", &ChipInfo::col_bias);
 
     class_<map<string, shared_ptr<Tile>>>("TileMap")
             .def(map_indexing_suite<map<string, shared_ptr<Tile>>, true>());
@@ -173,6 +176,8 @@ BOOST_PYTHON_MODULE (pytrellis)
             .def(vector_indexing_suite<CRAMDelta>());
 
     // From Tile.cpp
+    def("get_row_col_pair_from_chipsize", get_row_col_pair_from_chipsize);
+
     class_<vector<SiteInfo>>("SiteInfoVector")
             .def(vector_indexing_suite<vector<SiteInfo>>());
 

diff --git a/libtrellis/src/Tile.cpp b/libtrellis/src/Tile.cpp
@@ -3,8 +3,25 @@
 #include "Database.hpp"
 #include "BitDatabase.hpp"
 #include "TileConfig.hpp"
+#include "Util.hpp"
 
 namespace Trellis {
+// Regex to extract row/column from a tile name
+static const regex tile_rxcx_re(R"(R(\d+)C(\d+))");
+
+// Universal function to get a zero-indexed row/column pair.
+pair<int, int> get_row_col_pair_from_chipsize(string name, pair<int, int> chip_size, int bias) {
+    smatch m;
+    bool match;
+
+    match = regex_search(name, m, tile_rxcx_re);
+    if(match) {
+        return make_pair(stoi(m.str(1)), stoi(m.str(2)));
+    } else {
+        throw runtime_error(fmt("Could not extract position from " << name));
+    }
+}
+
 Tile::Tile(Trellis::TileInfo info, Trellis::Chip &parent) : info(info), cram(parent.cram.make_view(info.frame_offset,
                                                                                                    info.bit_offset,
                                                                                                    info.num_frames,