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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-…
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…linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  MIPS: IP27: Enable RAID5 module
  MIPS: TXx9: update defconfigs
  MIPS: NEC VR5500 processor support fixup
  MIPS: Fix build of non-CONFIG_SYSVIPC version of sys_32_ipc
torvalds committed Mar 12, 2009
2 parents 0789d8f + 0a7c808 commit 8c57a8f
Showing 9 changed files with 456 additions and 142 deletions.
2 changes: 1 addition & 1 deletion arch/mips/configs/ip27_defconfig
Original file line number Diff line number Diff line change
@@ -512,7 +512,7 @@ CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_RAID456=y
CONFIG_MD_RAID5_RESHAPE=y
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
265 changes: 188 additions & 77 deletions arch/mips/configs/jmr3927_defconfig

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319 changes: 259 additions & 60 deletions arch/mips/configs/rbtx49xx_defconfig

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3 changes: 2 additions & 1 deletion arch/mips/include/asm/hazards.h
Original file line number Diff line number Diff line change
@@ -138,7 +138,8 @@ do { \
__instruction_hazard(); \
} while (0)

#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_R5500)

/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
2 changes: 1 addition & 1 deletion arch/mips/include/asm/prefetch.h
Original file line number Diff line number Diff line change
@@ -26,7 +26,7 @@
* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
* current versions due to erratum G105.
*
* VR7701 only implements the Load prefetch.
* VR5500 (including VR5701 and VR7701) only implement load prefetch.
*
* Finally MIPS32 and MIPS64 implement all of the following hints.
*/
1 change: 1 addition & 0 deletions arch/mips/kernel/cpu-probe.c
Original file line number Diff line number Diff line change
@@ -149,6 +149,7 @@ void __init check_wait(void)
case CPU_R4650:
case CPU_R4700:
case CPU_R5000:
case CPU_R5500:
case CPU_NEVADA:
case CPU_4KC:
case CPU_4KEC:
2 changes: 1 addition & 1 deletion arch/mips/kernel/linux32.c
Original file line number Diff line number Diff line change
@@ -235,7 +235,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
#else

SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third,
u32, ptr, u32 fifth)
u32, ptr, u32, fifth)
{
return -ENOSYS;
}
3 changes: 2 additions & 1 deletion arch/mips/mm/page.c
Original file line number Diff line number Diff line change
@@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
*/
cache_line_size = cpu_dcache_line_size();
switch (current_cpu_type()) {
case CPU_R5500:
case CPU_TX49XX:
/* TX49 supports only Pref_Load */
/* These processors only support the Pref_Load. */
pref_bias_copy_load = 256;
break;

1 change: 1 addition & 0 deletions arch/mips/mm/tlbex.c
Original file line number Diff line number Diff line change
@@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_BCM4710:
case CPU_LOONGSON2:
case CPU_CAVIUM_OCTEON:
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
tlbw(p);

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