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Test for sc2135
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@ZigFisher
ZigFisher committed Mar 11, 2021
1 parent 09a1c84 commit febc289
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2 changes: 1 addition & 1 deletion hisi-osdrv1/binary/etc/sensors/sc1135_720p_line.ini
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Expand Up @@ -8,7 +8,7 @@ Mode =0 ;WDR_MODE_NONE = 0
;WDR_MODE_2To1_LINE = 2
;WDR_MODE_2To1_FRAME = 3
;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
DllFile =/usr/lib/libsns_sc1135.so ;sensor lib path
DllFile =/usr/lib/sensors/libsns_sc1135.so ;sensor lib path


[mode]
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260 changes: 260 additions & 0 deletions hisi-osdrv1/binary/etc/sensors/sc2135_i2c_dc_1080p_line.ini
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@@ -0,0 +1,260 @@
[sensor]
Sensor_type =sc2135 ;sensor name
Mode =0 ;WDR_MODE_NONE = 0
;WDR_MODE_BUILT_IN = 1
;WDR_MODE_2To1_LINE = 2
;WDR_MODE_2To1_FRAME = 3
;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
DllFile =/usr/lib/sensors/libsns_sc2135.so ;sensor lib path


[mode]
input_mode =4 ;INPUT_MODE_MIPI = 0
;INPUT_MODE_SUBLVDS = 1
;INPUT_MODE_LVDS = 2 ...etc

dev_attr = 2 ;mipi_dev_attr_t = 0
;lvds_dev_attr_t = 1
;NULL =2

[mipi]
;----------only for mipi_dev---------
data_type =-1 ;raw data type: 8/10/12/14 bit
;RAW_DATA_8BIT = 0
;RAW_DATA_10BIT = 1
;RAW_DATA_12BIT = 2
;RAW_DATA_14BIT = 3
lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable

[lvds]
;----------only for lvds_dev---------
img_size_w = -1 ;oringnal sensor input image size W
img_size_h = -1 ;oringnal sensor input image size H
wdr_mode = -1 ;HI_WDR_MODE_NONE =0
;HI_WDR_MODE_2F = 1
;HI_WDR_MODE_3F = 2
;HI_WDR_MODE_4F =3
sync_mode = -1 ;LVDS_SYNC_MODE_SOL = 0
;LVDS_SYNC_MODE_SAV = 1
raw_data_type = -1 ;RAW_DATA_8BIT = 0
;RAW_DATA_10BIT = 1
;RAW_DATA_12BIT = 2
;RAW_DATA_14BIT = 3
data_endian = -1 ;LVDS_ENDIAN_LITTLE = 0
;LVDS_ENDIAN_BIG = 1
sync_code_endian =-1 ;LVDS_ENDIAN_LITTLE = 0
;LVDS_ENDIAN_BIG = 1
lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable
lvds_lane_num = -1 ;LVDS_LANE_NUM
wdr_vc_num = -1 ;WDR_VC_NUM
sync_code_num = -1 ;SYNC_CODE_NUM
sync_code_0 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_1 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_2 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_3 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_4 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_5 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_6 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|
sync_code_7 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|

[isp_image]
Isp_x =0
Isp_y =0
Isp_W =1920
Isp_H =1080
Isp_FrameRate=30
Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3


[vi_dev]
Input_mod =2 ;VI_INPUT_MODE_BT656 = 0
;VI_INPUT_MODE_BT601,
;VI_INPUT_MODE_DIGITAL_CAMERA
Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
;VI_WORK_MODE_2Multiplex,
;VI_WORK_MODE_4Multiplex
Combine_mode =0 ;Y/C composite or separation mode
;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
;VI_COMBINE_SEPARATE, /*Separate mode */
Comp_mode =0 ;Component mode (single-component or dual-component)
;VI_COMP_MODE_SINGLE = 0, /*single component mode */
;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
Mask_num =2 ;Component mask
Mask_0 =0xFFF0000
Mask_1 =0x0
Scan_mode =1 ;VI_SCAN_INTERLACED = 0
;VI_SCAN_PROGRESSIVE,
Data_seq =2 ;data sequence (ONLY for YUV format)
;----2th component U/V sequence in bt1120
; VI_INPUT_DATA_VUVU = 0,
; VI_INPUT_DATA_UVUV,
;----input sequence for yuv
; VI_INPUT_DATA_UYVY = 0,
; VI_INPUT_DATA_VYUY,
; VI_INPUT_DATA_YUYV,
; VI_INPUT_DATA_YVYU

Vsync =1 ; vertical synchronization signal
;VI_VSYNC_FIELD = 0,
;VI_VSYNC_PULSE,
VsyncNeg=0 ;Polarity of the vertical synchronization signal
;VI_VSYNC_NEG_HIGH = 0,
;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
Hsync =0 ;Attribute of the horizontal synchronization signal
;VI_HSYNC_VALID_SINGNAL = 0,
;VI_HSYNC_PULSE,
HsyncNeg =0 ;Polarity of the horizontal synchronization signal
;VI_HSYNC_NEG_HIGH = 0,
;VI_HSYNC_NEG_LOW
VsyncValid =0 ;Attribute of the valid vertical synchronization signal
;VI_VSYNC_NORM_PULSE = 0,
;VI_VSYNC_VALID_SINGAL,
VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
;VI_VSYNC_VALID_NEG_HIGH = 0,
;VI_VSYNC_VALID_NEG_LOW
Timingblank_HsyncHfb =0 ;Horizontal front blanking width
Timingblank_HsyncAct =1920 ;Horizontal effetive width
Timingblank_HsyncHbb =0 ;Horizontal back blanking width
Timingblank_VsyncVfb =0 ;Vertical front blanking height
Timingblank_VsyncVact =1080 ;Vertical effetive width
Timingblank_VsyncVbb=0 ;Vertical back blanking height
Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)

;----- only for bt656 ----------
FixCode =0 ;BT656_FIXCODE_1 = 0,
;BT656_FIXCODE_0
FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0
;BT656_FIELD_POLAR_NSTD
DataPath =1 ;ISP enable or bypass
;VI_PATH_BYPASS = 0,/* ISP bypass */
;VI_PATH_ISP = 1,/* ISP enable */
;VI_PATH_RAW = 2,/* Capture raw data, for debug */
InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
DevRect_x=0 ;
DevRect_y=0 ;
DevRect_w=1920 ;
DevRect_h=1080 ;

[vi_chn]
CapRect_X =0
CapRect_Y =0
CapRect_Width=1920
CapRect_Height=1080
DestSize_Width=1920
DestSize_Height=1080
CapSel =2 ;Frame/field select. ONLY used in interlaced mode
;VI_CAPSEL_TOP = 0, /* top field */
;VI_CAPSEL_BOTTOM, /* bottom field */
;VI_CAPSEL_BOTH, /* top and bottom field */

PixFormat =23;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22
;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc
CompressMode =0 ;COMPRESS_MODE_NONE = 0
;COMPRESS_MODE_SEG =1 ...etc

;SrcFrameRate=-1 ;Source frame rate. -1: not controll
;FrameRate =-1 ;Target frame rate. -1: not controll

SrcFrameRate=30 ;Source frame rate. -1: not controll
FrameRate =30 ;Target frame rate. -1: not controll
[vpss_group]
Vpss_DciEn =FALSE
Vpss_IeEn =FALSE
Vpss_NrEn =TRUE
Vpss_HistEn =FALSE
Vpss_DieMode=1 ;Define de-interlace mode
;VPSS_DIE_MODE_AUTO = 0,
;VPSS_DIE_MODE_NODIE = 1,
;VPSS_DIE_MODE_DIE = 2,

[vpss_corp]
Crop_enable =FALSE
Coordinate =1 ;VPSS_CROP_RATIO_COOR = 0, /*Ratio coordinate*/
;VPSS_CROP_ABS_COOR = 1 /*Absolute coordinate*/
Crop_X =128
Crop_Y =128
Crop_W =1158
Crop_H =562

[vpss_chn]
Vpss_W =1920
Vpss_H =1080
CompressMode=0 ;COMPRESS_MODE_NONE = 0
;COMPRESS_MODE_SEG =1 ...etc
Mirror =FALSE;Whether to mirror
Flip =FALSE;Whether to flip

[vb_conf]
VbCnt=5
#VbCnt=2
vbTimes=15

[venc_comm]
venc_chn =1 ;create venc chn number;(0,2]
BufCnt = 1 ;network meida-trans bufcnt

[venc_0]
PicWidth =1920
PicHeight =1080
Profile =2
RcMode =VENC_RC_MODE_H264CBR

Gop =50
StatTime =2
ViFrmRate =30
TargetFrmRate=15
;----- only for VENC_RC_MODE_H264CBR ----------
BitRate=4096
FluctuateLevel=1
;----- only for VENC_RC_MODE_H264VBR ----------
MaxBitRate =10000

MaxQp=32
MinQp=24
;----- only for VENC_RC_MODE_H264FIXQP ----------
IQp=45

PQp=40

[venc_1]
PicWidth =1920
PicHeight =1080
Profile =2
RcMode =VENC_RC_MODE_H264CBR

Gop =50
StatTime =2
ViFrmRate =30
TargetFrmRate=15
;----- only for VENC_RC_MODE_H264CBR ----------
BitRate=4096
FluctuateLevel=1
;----- only for VENC_RC_MODE_H264VBR ----------
MaxBitRate =10000

MaxQp=32

MinQp=24
;----- only for VENC_RC_MODE_H264FIXQP ----------
IQp=40

PQp=45

[bind]
ViDev =0
ViChn =0
VpssGrp =0
VpssChn = 0
VoDev =0
VoChn =0
ViSnapChn =0
VpssSnapGrp=0
VpssSnapChn=1
VencSnapGrp=1
VencSnapChn=3
Binary file added hisi-osdrv1/binary/lib/sensors/libsns_sc2135.so
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27 changes: 16 additions & 11 deletions hisi-osdrv1/script/load_hisilicon
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Expand Up @@ -74,42 +74,47 @@ insert_sns()
insmod ssp_ad9020.ko;
;;

hm1375)
devmem 0x20030030 32 0x1; # Sensor clock 24 MHz
;;

icx692)
devmem 0x200f000c 32 0x1; # pinmux SPI0
devmem 0x200f0010 32 0x1; # pinmux SPI0
devmem 0x200f0014 32 0x1; # pinmux SPI0
insmod ssp_ad9020.ko;
;;

mn34031|mn34041)
imx104|imx122|imx138|imx222|imx222_spi_dc|imx322)
devmem 0x200f000c 32 0x1; # pinmux SPI0
devmem 0x200f0010 32 0x1; # pinmux SPI0
devmem 0x200f0014 32 0x1; # pinmux SPI0
devmem 0x20030030 32 0x5; # Sensor clock 27MHz
insmod ssp_pana.ko;
devmem 0x20030030 32 0x6; # Sensor clock 37.125 MHz
insmod ssp_sony.ko;
;;

imx104|imx122|imx138|imx222|imx222_spi_dc|imx322)
mn34031|mn34041)
devmem 0x200f000c 32 0x1; # pinmux SPI0
devmem 0x200f0010 32 0x1; # pinmux SPI0
devmem 0x200f0014 32 0x1; # pinmux SPI0
devmem 0x20030030 32 0x6; # Sensor clock 37.125 MHz
insmod ssp_sony.ko;
devmem 0x20030030 32 0x5; # Sensor clock 27MHz
insmod ssp_pana.ko;
;;

ov9712|ov9712_i2c_dc|soih22|ov2710)
mt9p006)
devmem 0x20030030 32 0x1; # Sensor clock 24 MHz
devmem 0x2003002c 32 0x6a; # VI input associated clock phase reversed
insmod ssp_ad9020.ko;
;;

mt9p006)
ov9712|ov9712_i2c_dc|soih22|ov2710)
devmem 0x20030030 32 0x1; # Sensor clock 24 MHz
devmem 0x2003002c 32 0x6a; # VI input associated clock phase reversed
insmod ssp_ad9020.ko;
;;

hm1375)
devmem 0x20030030 32 0x1; # Sensor clock 24 MHz
sc2135|sc2135_i2c_dc)
devmem 0x20030030 32 0x5; # Sensor clock 27 MHz
insmod ssp_ad9020.ko;
;;

*)
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