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Merge tag 'drm-misc-next-2024-10-31' of https://gitlab.freedesktop.or…
…g/drm/misc/kernel into drm-next drm-misc-next for v6.13: All of the previous pull request, with MORE! Core Changes: - Update documentation for scheduler start/stop and job init. - Add dedede and sm8350-hdk hardware to ci runs. Driver Changes: - Small fixes and cleanups to panfrost, omap, nouveau, ivpu, zynqmp, v3d, panthor docs, and leadtek-ltk050h3146w. - Crashdump support for qaic. - Support DP compliance in zynqmp. - Add Samsung S6E88A0-AMS427AP24 panel. Signed-off-by: Dave Airlie <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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65
Documentation/devicetree/bindings/display/panel/samsung,s6e88a0-ams427ap24.yaml
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| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/display/panel/samsung,s6e88a0-ams427ap24.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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| title: Samsung AMS427AP24 panel with S6E88A0 controller | ||
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| maintainers: | ||
| - Jakob Hauser <[email protected]> | ||
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| allOf: | ||
| - $ref: panel-common.yaml# | ||
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| properties: | ||
| compatible: | ||
| const: samsung,s6e88a0-ams427ap24 | ||
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| reg: | ||
| maxItems: 1 | ||
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| port: true | ||
| reset-gpios: true | ||
| flip-horizontal: true | ||
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| vdd3-supply: | ||
| description: core voltage supply | ||
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| vci-supply: | ||
| description: voltage supply for analog circuits | ||
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| required: | ||
| - compatible | ||
| - reg | ||
| - port | ||
| - reset-gpios | ||
| - vdd3-supply | ||
| - vci-supply | ||
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| additionalProperties: false | ||
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| examples: | ||
| - | | ||
| #include <dt-bindings/gpio/gpio.h> | ||
| dsi { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| panel@0 { | ||
| compatible = "samsung,s6e88a0-ams427ap24"; | ||
| reg = <0>; | ||
| vdd3-supply = <&pm8916_l17>; | ||
| vci-supply = <&pm8916_l6>; | ||
| reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; | ||
| flip-horizontal; | ||
| port { | ||
| panel_in: endpoint { | ||
| remote-endpoint = <&mdss_dsi0_out>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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188
Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml
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| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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| title: Rockchip DW HDMI QP TX Encoder | ||
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| maintainers: | ||
| - Cristian Ciocaltea <[email protected]> | ||
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| description: | | ||
| Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller | ||
| IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block, providing the | ||
| following features, among others: | ||
| * Fixed Rate Link (FRL) | ||
| * Display Stream Compression (DSC) | ||
| * 4K@120Hz and 8K@60Hz video modes | ||
| * Variable Refresh Rate (VRR) including Quick Media Switching (QMS) | ||
| * Fast Vactive (FVA) | ||
| * SCDC I2C DDC access | ||
| * Multi-stream audio | ||
| * Enhanced Audio Return Channel (EARC) | ||
| allOf: | ||
| - $ref: /schemas/sound/dai-common.yaml# | ||
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| properties: | ||
| compatible: | ||
| enum: | ||
| - rockchip,rk3588-dw-hdmi-qp | ||
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| reg: | ||
| maxItems: 1 | ||
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| clocks: | ||
| items: | ||
| - description: Peripheral/APB bus clock | ||
| - description: EARC RX biphase clock | ||
| - description: Reference clock | ||
| - description: Audio interface clock | ||
| - description: TMDS/FRL link clock | ||
| - description: Video datapath clock | ||
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| clock-names: | ||
| items: | ||
| - const: pclk | ||
| - const: earc | ||
| - const: ref | ||
| - const: aud | ||
| - const: hdp | ||
| - const: hclk_vo1 | ||
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| interrupts: | ||
| items: | ||
| - description: AVP Unit interrupt | ||
| - description: CEC interrupt | ||
| - description: eARC RX interrupt | ||
| - description: Main Unit interrupt | ||
| - description: HPD interrupt | ||
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| interrupt-names: | ||
| items: | ||
| - const: avp | ||
| - const: cec | ||
| - const: earc | ||
| - const: main | ||
| - const: hpd | ||
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| phys: | ||
| maxItems: 1 | ||
| description: The HDMI/eDP PHY | ||
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| ports: | ||
| $ref: /schemas/graph.yaml#/properties/ports | ||
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| properties: | ||
| port@0: | ||
| $ref: /schemas/graph.yaml#/properties/port | ||
| description: Video port for RGB/YUV input. | ||
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| port@1: | ||
| $ref: /schemas/graph.yaml#/properties/port | ||
| description: Video port for HDMI/eDP output. | ||
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| required: | ||
| - port@0 | ||
| - port@1 | ||
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| power-domains: | ||
| maxItems: 1 | ||
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| resets: | ||
| maxItems: 2 | ||
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| reset-names: | ||
| items: | ||
| - const: ref | ||
| - const: hdp | ||
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| "#sound-dai-cells": | ||
| const: 0 | ||
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| rockchip,grf: | ||
| $ref: /schemas/types.yaml#/definitions/phandle | ||
| description: | ||
| Some HDMI QP related data is accessed through SYS GRF regs. | ||
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| rockchip,vo-grf: | ||
| $ref: /schemas/types.yaml#/definitions/phandle | ||
| description: | ||
| Additional HDMI QP related data is accessed through VO GRF regs. | ||
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| required: | ||
| - compatible | ||
| - reg | ||
| - clocks | ||
| - clock-names | ||
| - interrupts | ||
| - interrupt-names | ||
| - phys | ||
| - ports | ||
| - resets | ||
| - reset-names | ||
| - rockchip,grf | ||
| - rockchip,vo-grf | ||
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| unevaluatedProperties: false | ||
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| examples: | ||
| - | | ||
| #include <dt-bindings/clock/rockchip,rk3588-cru.h> | ||
| #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| #include <dt-bindings/interrupt-controller/irq.h> | ||
| #include <dt-bindings/power/rk3588-power.h> | ||
| #include <dt-bindings/reset/rockchip,rk3588-cru.h> | ||
| soc { | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| hdmi@fde80000 { | ||
| compatible = "rockchip,rk3588-dw-hdmi-qp"; | ||
| reg = <0x0 0xfde80000 0x0 0x20000>; | ||
| clocks = <&cru PCLK_HDMITX0>, | ||
| <&cru CLK_HDMITX0_EARC>, | ||
| <&cru CLK_HDMITX0_REF>, | ||
| <&cru MCLK_I2S5_8CH_TX>, | ||
| <&cru CLK_HDMIHDP0>, | ||
| <&cru HCLK_VO1>; | ||
| clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; | ||
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, | ||
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, | ||
| <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, | ||
| <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, | ||
| <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| interrupt-names = "avp", "cec", "earc", "main", "hpd"; | ||
| phys = <&hdptxphy_hdmi0>; | ||
| power-domains = <&power RK3588_PD_VO1>; | ||
| resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; | ||
| reset-names = "ref", "hdp"; | ||
| rockchip,grf = <&sys_grf>; | ||
| rockchip,vo-grf = <&vo1_grf>; | ||
| #sound-dai-cells = <0>; | ||
| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| port@0 { | ||
| reg = <0>; | ||
| hdmi0_in_vp0: endpoint { | ||
| remote-endpoint = <&vp0_out_hdmi0>; | ||
| }; | ||
| }; | ||
| port@1 { | ||
| reg = <1>; | ||
| hdmi0_out_con0: endpoint { | ||
| remote-endpoint = <&hdmi_con0_in>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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