KVM: x86: ioapic: Don't fire level irq when Remote IRR set

Avoid firing a level-triggered interrupt that has the Remote IRR bit set, because that means that some CPU is already processing it. The Remote IRR bit will be cleared after an EOI and the interrupt will refire if the irq line is still asserted. This behavior is aligned with QEMU's IOAPIC implementation that was introduced by commit f99b86b ("x86: ioapic: ignore level irq during processing") in QEMU. Signed-off-by: Nikita Leshenko <[email protected]> Reviewed-by: Liran Alon <[email protected]> Signed-off-by: Konrad Rzeszutek Wilk <[email protected]> Reviewed-by: Wanpeng Li <[email protected]> Signed-off-by: Radim Krčmář <[email protected]>
sfionov · Nov 17, 2017 · da3fe7b · da3fe7b
1 parent 0fc5a36
commit da3fe7b
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
@@ -323,7 +323,9 @@ static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
 	struct kvm_lapic_irq irqe;
 	int ret;
 
-	if (entry->fields.mask)
+	if (entry->fields.mask ||
+	    (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG &&
+	    entry->fields.remote_irr))
 		return -1;
 
 	ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "