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Expose EnableISA knobs in release build (dotnet/coreclr#20501)
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Commit migrated from dotnet/coreclr@58f6d24
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@FeiPengIntel @tannergooding
FeiPengIntel authored and tannergooding committed Oct 24, 2018
1 parent 7804d80 commit 9eb2cb4
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Showing 3 changed files with 70 additions and 64 deletions.
90 changes: 52 additions & 38 deletions src/coreclr/src/jit/compiler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2321,58 +2321,72 @@ const char* Compiler::compLocalVarName(unsigned varNum, unsigned offs)
#ifdef _TARGET_XARCH_
static bool configEnableISA(InstructionSet isa)
{
#ifdef DEBUG
switch (isa)
{
case InstructionSet_AVX2:
if (JitConfig.EnableAVX2() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_AVX:
if (JitConfig.EnableAVX() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_SSE42:
if (JitConfig.EnableSSE42() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_SSE41:
if (JitConfig.EnableSSE41() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_SSSE3:
if (JitConfig.EnableSSSE3() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_SSE3:
if (JitConfig.EnableSSE3() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_SSE2:
if (JitConfig.EnableSSE2() == 0)
{
return false;
}
__fallthrough;
case InstructionSet_SSE:
return JitConfig.EnableSSE() != 0;
case InstructionSet_SSE2:
return JitConfig.EnableSSE2() != 0;
case InstructionSet_SSE3:
return JitConfig.EnableSSE3() != 0;
case InstructionSet_SSSE3:
return JitConfig.EnableSSSE3() != 0;
case InstructionSet_SSE41:
return JitConfig.EnableSSE41() != 0;
case InstructionSet_SSE42:
return JitConfig.EnableSSE42() != 0;
case InstructionSet_AVX:
return JitConfig.EnableAVX() != 0;
case InstructionSet_FMA:
return JitConfig.EnableFMA() != 0;
case InstructionSet_AVX2:
return JitConfig.EnableAVX2() != 0;

case InstructionSet_AES:
return JitConfig.EnableAES() != 0;
// TODO: BMI1/BMI2 actually don't depend on AVX, they depend on the VEX encoding; which is currently controlled
// by InstructionSet_AVX
case InstructionSet_BMI1:
return JitConfig.EnableBMI1() != 0;
return JitConfig.EnableBMI1() != 0 && configEnableISA(InstructionSet_AVX);
case InstructionSet_BMI2:
return JitConfig.EnableBMI2() != 0;
return JitConfig.EnableBMI2() != 0 && configEnableISA(InstructionSet_AVX);
case InstructionSet_FMA:
return JitConfig.EnableFMA() != 0 && configEnableISA(InstructionSet_AVX);
case InstructionSet_AES:
return JitConfig.EnableAES() != 0 && configEnableISA(InstructionSet_SSE2);
case InstructionSet_LZCNT:
return JitConfig.EnableLZCNT() != 0;
case InstructionSet_PCLMULQDQ:
return JitConfig.EnablePCLMULQDQ() != 0;
return JitConfig.EnablePCLMULQDQ() != 0 && configEnableISA(InstructionSet_SSE2);
case InstructionSet_POPCNT:
return JitConfig.EnablePOPCNT() != 0;
return JitConfig.EnablePOPCNT() != 0 && configEnableISA(InstructionSet_SSE42);
default:
return false;
}
#else
// We have a retail config switch that can disable instruction sets reliant on the VEX encoding
switch (isa)
{
case InstructionSet_AVX:
case InstructionSet_FMA:
case InstructionSet_AVX2:
case InstructionSet_BMI1:
case InstructionSet_BMI2:
return JitConfig.EnableAVX() != 0;

default:
return true;
}
#endif
}
#endif // _TARGET_XARCH_

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6 changes: 1 addition & 5 deletions src/coreclr/src/jit/ee_il_dll.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -393,11 +393,7 @@ unsigned CILJit::getMaxIntrinsicSIMDVectorLength(CORJIT_FLAGS cpuCompileFlags)
if (!jitFlags.IsSet(JitFlags::JIT_FLAG_PREJIT) && jitFlags.IsSet(JitFlags::JIT_FLAG_FEATURE_SIMD) &&
jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX2))
{
if (JitConfig.EnableAVX() != 0
#ifdef DEBUG
&& JitConfig.EnableAVX2() != 0
#endif
)
if (JitConfig.EnableAVX() != 0 && JitConfig.EnableAVX2() != 0)
{
if (GetJitTls() != nullptr && JitTls::GetCompiler() != nullptr)
{
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38 changes: 17 additions & 21 deletions src/coreclr/src/jit/jitconfigvalues.h
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Original file line number Diff line number Diff line change
Expand Up @@ -205,24 +205,6 @@ CONFIG_STRING(NgenDumpIRPhase, W("NgenDumpIRPhase")) // Same as JitDumpIRPhase
///
/// JIT Hardware Intrinsics
///
#if defined(_TARGET_X86_) || defined(_TARGET_AMD64_)
CONFIG_INTEGER(EnableSSE, W("EnableSSE"), 1) // Enable SSE
CONFIG_INTEGER(EnableSSE2, W("EnableSSE2"), 1) // Enable SSE2
CONFIG_INTEGER(EnableSSE3, W("EnableSSE3"), 1) // Enable SSE3
CONFIG_INTEGER(EnableSSSE3, W("EnableSSSE3"), 1) // Enable SSSE3
CONFIG_INTEGER(EnableSSE41, W("EnableSSE41"), 1) // Enable SSE41
CONFIG_INTEGER(EnableSSE42, W("EnableSSE42"), 1) // Enable SSE42
// EnableAVX is already defined for DEBUG and non-DEBUG mode both
CONFIG_INTEGER(EnableAVX2, W("EnableAVX2"), 1) // Enable AVX2

CONFIG_INTEGER(EnableAES, W("EnableAES"), 1) // Enable AES
CONFIG_INTEGER(EnableBMI1, W("EnableBMI1"), 1) // Enable BMI1
CONFIG_INTEGER(EnableBMI2, W("EnableBMI2"), 1) // Enable BMI2
CONFIG_INTEGER(EnableFMA, W("EnableFMA"), 1) // Enable FMA
CONFIG_INTEGER(EnableLZCNT, W("EnableLZCNT"), 1) // Enable AES
CONFIG_INTEGER(EnablePCLMULQDQ, W("EnablePCLMULQDQ"), 1) // Enable PCLMULQDQ
CONFIG_INTEGER(EnablePOPCNT, W("EnablePOPCNT"), 1) // Enable POPCNT
#endif // defined(_TARGET_X86_) || defined(_TARGET_AMD64_)
CONFIG_INTEGER(EnableIncompleteISAClass, W("EnableIncompleteISAClass"), 0) // Enable testing not-yet-implemented
// intrinsic classes
#endif // defined(DEBUG)
Expand Down Expand Up @@ -251,11 +233,25 @@ CONFIG_INTEGER(EnableSSE3_4, W("EnableSSE3_4"), 1) // Enable SSE3, SSSE3, SSE 4.
#if defined(_TARGET_AMD64_) || defined(_TARGET_X86_)
// Enable AVX instruction set for wide operations as default. When both AVX and SSE3_4 are set, we will use the most
// capable instruction set available which will prefer AVX over SSE3/4.
CONFIG_INTEGER(EnableAVX, W("EnableAVX"), 1)
#else // !defined(_TARGET_AMD64_) && !defined(_TARGET_X86_)
CONFIG_INTEGER(EnableSSE, W("EnableSSE"), 1) // Enable SSE
CONFIG_INTEGER(EnableSSE2, W("EnableSSE2"), 1) // Enable SSE2
CONFIG_INTEGER(EnableSSE3, W("EnableSSE3"), 1) // Enable SSE3
CONFIG_INTEGER(EnableSSSE3, W("EnableSSSE3"), 1) // Enable SSSE3
CONFIG_INTEGER(EnableSSE41, W("EnableSSE41"), 1) // Enable SSE41
CONFIG_INTEGER(EnableSSE42, W("EnableSSE42"), 1) // Enable SSE42
CONFIG_INTEGER(EnableAVX, W("EnableAVX"), 1) // Enable AVX
CONFIG_INTEGER(EnableAVX2, W("EnableAVX2"), 1) // Enable AVX2
CONFIG_INTEGER(EnableFMA, W("EnableFMA"), 1) // Enable FMA
CONFIG_INTEGER(EnableAES, W("EnableAES"), 1) // Enable AES
CONFIG_INTEGER(EnableBMI1, W("EnableBMI1"), 1) // Enable BMI1
CONFIG_INTEGER(EnableBMI2, W("EnableBMI2"), 1) // Enable BMI2
CONFIG_INTEGER(EnableLZCNT, W("EnableLZCNT"), 1) // Enable AES
CONFIG_INTEGER(EnablePCLMULQDQ, W("EnablePCLMULQDQ"), 1) // Enable PCLMULQDQ
CONFIG_INTEGER(EnablePOPCNT, W("EnablePOPCNT"), 1) // Enable POPCNT
#else // !defined(_TARGET_AMD64_) && !defined(_TARGET_X86_)
// Enable AVX instruction set for wide operations as default
CONFIG_INTEGER(EnableAVX, W("EnableAVX"), 0)
#endif // !defined(_TARGET_AMD64_) && !defined(_TARGET_X86_)
#endif // !defined(_TARGET_AMD64_) && !defined(_TARGET_X86_)
///
/// JIT
///
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