Reverting NFC changes from r218050. Instead, the warning was disabled…

… for GCC in r218059, so these changes are no longer required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218062 91177308-0d34-0410-b5e6-96231b3b80d8
sigma-random · Sep 18, 2014 · c21e4e1 · c21e4e1
1 parent d80c086
commit c21e4e1
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Showing 12 changed files with 0 additions and 14 deletions.
diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h
@@ -31,7 +31,6 @@ class AArch64TargetMachine : public LLVMTargetMachine {
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL, bool IsLittleEndian);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const AArch64Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
@@ -32,7 +32,6 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
                        CodeGenOpt::Level OL,
                        bool isLittle);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   /// \brief Register ARM analysis passes with a pass manager.

diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -31,7 +31,6 @@ class HexagonTargetMachine : public LLVMTargetMachine {
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const HexagonSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h
@@ -32,7 +32,6 @@ class MSP430TargetMachine : public LLVMTargetMachine {
                       Reloc::Model RM, CodeModel::Model CM,
                       CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const MSP430Subtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
@@ -39,7 +39,6 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   void addAnalysisPasses(PassManagerBase &PM) override;
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const MipsSubtarget *getSubtargetImpl() const override {
     if (Subtarget)
       return Subtarget;

diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -35,7 +35,6 @@ class NVPTXTargetMachine : public LLVMTargetMachine {
                      const TargetOptions &Options, Reloc::Model RM,
                      CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   ManagedStringPool *getManagedStrPool() const {

diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -32,7 +32,6 @@ class PPCTargetMachine : public LLVMTargetMachine {
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration

diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h
@@ -33,8 +33,6 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
                       StringRef CPU, TargetOptions Options, Reloc::Model RM,
                       CodeModel::Model CM, CodeGenOpt::Level OL);
   ~AMDGPUTargetMachine();
-
-  using LLVMTargetMachine::getSubtargetImpl;
   const AMDGPUSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
@@ -28,7 +28,6 @@ class SparcTargetMachine : public LLVMTargetMachine {
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL, bool is64bit);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration

diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -32,7 +32,6 @@ class SystemZTargetMachine : public LLVMTargetMachine {
                        CodeGenOpt::Level OL);
 
   // Override TargetMachine.
-  using LLVMTargetMachine::getSubtargetImpl;
   const SystemZSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }

diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
@@ -31,8 +31,6 @@ class X86TargetMachine final : public LLVMTargetMachine {
                    StringRef CPU, StringRef FS, const TargetOptions &Options,
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
-
-  using LLVMTargetMachine::getSubtargetImpl;
   const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   /// \brief Register X86 analysis passes with a pass manager.

diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h
@@ -27,7 +27,6 @@ class XCoreTargetMachine : public LLVMTargetMachine {
                      Reloc::Model RM, CodeModel::Model CM,
                      CodeGenOpt::Level OL);
 
-  using LLVMTargetMachine::getSubtargetImpl;
   const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
 
   // Pass Pipeline Configuration