bump the cortex-m-rt to v0.4.0

.cargo/config

@@ -2,34 +2,38 @@
 runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "linker=arm-none-eabi-ld",
-  "-Z", "linker-flavor=ld",
-  "-Z", "thinlto=no",
+  "-C", "linker=lld",
+  "-Z", "linker-flavor=ld.lld",
+  # "-C", "linker=arm-none-eabi-ld",
+  # "-Z", "linker-flavor=ld",
 ]
 
 [target.thumbv7m-none-eabi]
 runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "linker=arm-none-eabi-ld",
-  "-Z", "linker-flavor=ld",
-  "-Z", "thinlto=no",
+  "-C", "linker=lld",
+  "-Z", "linker-flavor=ld.lld",
+  # "-C", "linker=arm-none-eabi-ld",
+  # "-Z", "linker-flavor=ld",
 ]
 
 [target.thumbv7em-none-eabi]
 runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "linker=arm-none-eabi-ld",
-  "-Z", "linker-flavor=ld",
-  "-Z", "thinlto=no",
+  "-C", "linker=lld",
+  "-Z", "linker-flavor=ld.lld",
+  # "-C", "linker=arm-none-eabi-ld",
+  # "-Z", "linker-flavor=ld",
 ]
 
 [target.thumbv7em-none-eabihf]
 runner = 'arm-none-eabi-gdb'
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "linker=arm-none-eabi-ld",
-  "-Z", "linker-flavor=ld",
-  "-Z", "thinlto=no",
+  "-C", "linker=lld",
+  "-Z", "linker-flavor=ld.lld",
+  # "-C", "linker=arm-none-eabi-ld",
+  # "-Z", "linker-flavor=ld",
 ]

.travis.yml

@@ -0,0 +1,43 @@
+language: rust
+
+matrix:
+  include:
+    - env: TARGET=thumbv6m-none-eabi
+      rust: nightly
+
+    - env: TARGET=thumbv7m-none-eabi
+      rust: nightly
+
+    - env: TARGET=thumbv7em-none-eabi
+      rust: nightly
+
+    - env: TARGET=thumbv7em-none-eabihf
+      rust: nightly
+
+before_install: set -e
+
+install:
+  - bash ci/install.sh
+
+script:
+  - bash ci/script.sh
+
+after_script: set +e
+
+after_success:
+  - bash ci/after_success.sh
+
+cache: cargo
+
+before_cache:
+  # Travis can't cache files that are not readable by "others"
+  - chmod -R a+r $HOME/.cargo
+
+branches:
+  only:
+    - staging
+    - trying
+
+notifications:
+  email:
+    on_success: never

CHANGELOG.md

@@ -5,6 +5,12 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.2.7] - 2018-04-24
+
+### Changed
+
+- Bumped the dependency of `cortex-m-rt` to v0.4.0.
+
 ## [v0.2.6] - 2018-04-09
 
 ### Changed
@@ -143,7 +149,8 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 - Initial release
 
-[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...HEAD
+[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.7...HEAD
+[v0.2.7]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...v0.2.7
 [v0.2.6]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.5...v0.2.6
 [v0.2.5]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.4...v0.2.5
 [v0.2.4]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.3...v0.2.4

Cargo.toml

@@ -6,25 +6,24 @@ keywords = ["arm", "cortex-m", "template"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m-quickstart"
 repository = "https://github.com/japaric/cortex-m-quickstart"
-version = "0.2.6"
+version = "0.2.7"
 
 [dependencies]
 cortex-m = "0.4.0"
+cortex-m-rt = "0.4.0"
 cortex-m-semihosting = "0.2.0"
-# alloc-cortex-m release doesn't use linked_list_allocator v0.5.0 yet.
+panic-abort = "0.1.1"
+panic-semihosting = "0.1.0"
+panic-itm = "0.1.0"
 # Uncomment for the allocator example.
-#alloc-cortex-m = "0.3.2"
-
-[dependencies.cortex-m-rt]
-version = "0.3.15"
-# Comment for the panic example.
-features = ["abort-on-panic"]
+#alloc-cortex-m = "0.3.3"
 
 # Uncomment for the device example.
 # [dependencies.stm32f103xx]
 # features = ["rt"]
-# version = "0.8.0"
+# version = "0.9.0"
 
 [profile.release]
 debug = true
 lto = true
+opt-level = "s"

LICENSE-MIT

@@ -1,4 +1,4 @@
-Copyright (c) 2017 {{toml-escape author}}
+Copyright (c) 2018
 
 Permission is hereby granted, free of charge, to any
 person obtaining a copy of this software and associated

bors.toml

@@ -0,0 +1,3 @@
+status = [
+  "continuous-integration/travis-ci/push",
+]

ci/install.sh

@@ -0,0 +1,9 @@
+set -euxo pipefail
+
+main() {
+    rustup target add $TARGET
+
+    cargo install cargo-edit || true
+}
+
+main

ci/script.sh

@@ -0,0 +1,57 @@
+set -euxo pipefail
+
+main() {
+    local td=$(mktemp -d)
+
+    git clone . $td
+    pushd $td
+
+    cat >memory.x <<'EOF'
+MEMORY
+{
+  /* NOTE K = KiBi = 1024 bytes */
+  FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM : ORIGIN = 0x20000000, LENGTH = 40K
+}
+EOF
+
+    local examples=(
+        crash
+        # device
+        hello
+        itm
+        override-exception-handler
+        panic
+    )
+    for ex in "${examples[@]}"; do
+        cargo build --target $TARGET --example $ex
+        cargo build --target $TARGET --example $ex --release
+    done
+
+    cargo add alloc-cortex-m
+
+    cargo build --target $TARGET --example allocator
+    cargo build --target $TARGET --example allocator --release
+
+    examples+=( allocator )
+
+    if [ $TARGET = thumbv7m-none-eabi ]; then
+        cat >>Cargo.toml <<'EOF'
+[dependencies.stm32f103xx]
+features = ["rt"]
+version = "0.9.0"
+EOF
+
+        cargo build --target $TARGET --example device
+        cargo build --target $TARGET --example device --release
+
+        examples+=( device )
+    fi
+
+    IFS=,;eval arm-none-eabi-size target/$TARGET/release/examples/"{${examples[*]}}"
+
+    popd
+    rm -rf $td
+}
+
+main

examples/allocator.rs

@@ -1,7 +1,6 @@
 //! How to use the heap and a dynamic memory allocator
 //!
-//! This example depends on the alloc-cortex-m crate so you'll have to add it
-//! to your Cargo.toml:
+//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
 //!
 //! ``` text
 //! # or edit the Cargo.toml file manually
@@ -11,8 +10,8 @@
 //! ---
 
 #![feature(alloc)]
-#![feature(used)]
 #![feature(global_allocator)]
+#![feature(used)]
 #![no_std]
 
 // This is the allocator crate; you can use a different one
@@ -22,26 +21,27 @@ extern crate alloc;
 extern crate cortex_m;
 extern crate cortex_m_rt;
 extern crate cortex_m_semihosting;
+extern crate panic_abort; // panicking behavior
 
 use core::fmt::Write;
 
+use alloc_cortex_m::CortexMHeap;
 use cortex_m::asm;
 use cortex_m_semihosting::hio;
-use alloc_cortex_m::CortexMHeap;
 
 #[global_allocator]
 static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
 
 extern "C" {
     static mut _sheap: u32;
-    static mut _eheap: u32;
 }
 
+const HEAP_SIZE: usize = 1024; // in bytes
+
 fn main() {
     // Initialize the allocator
     let start = unsafe { &mut _sheap as *mut u32 as usize };
-    let end = unsafe { &mut _eheap as *mut u32 as usize };
-    unsafe { ALLOCATOR.init(start, end - start) }
+    unsafe { ALLOCATOR.init(start, HEAP_SIZE) }
 
     // Growable array allocated on the heap
     let xs = vec![0, 1, 2];

examples/crash.rs

@@ -1,12 +1,11 @@
 //! Debugging a crash (exception)
 //!
-//! The `cortex-m-rt` crate provides functionality for this through a default
-//! exception handler. When an exception is hit, the default handler will
-//! trigger a breakpoint and in this debugging context the stacked registers
-//! are accessible.
+//! The `cortex-m-rt` crate provides functionality for this through a default exception handler.
+//! When an exception is hit, the default handler will trigger a breakpoint and in this debugging
+//! context the stacked registers are accessible.
 //!
-//! In you run the example below, you'll be able to inspect the state of your
-//! program under the debugger using these commands:
+//! In you run the example below, you'll be able to inspect the state of your program under the
+//! debugger using these commands:
 //!
 //! ``` text
 //! (gdb) # Exception frame = program state during the crash
@@ -63,6 +62,7 @@
 
 extern crate cortex_m;
 extern crate cortex_m_rt;
+extern crate panic_abort; // panicking behavior
 
 use core::ptr;
 

examples/device.rs

@@ -1,25 +1,22 @@
 //! Using a device crate
 //!
-//! Crates generated using [`svd2rust`] are referred to as device crates. These
-//! crates provides an API to access the peripherals of a device. When you
-//! depend on one of these crates and the "rt" feature is enabled you don't need
-//! link to the cortex-m-rt crate.
+//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
+//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
+//! feature is enabled you don't need link to the cortex-m-rt crate.
 //!
 //! [`svd2rust`]: https://crates.io/crates/svd2rust
 //!
-//! Device crates also provide an `interrupt!` macro to register interrupt
-//! handlers.
+//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
 //!
-//! This example depends on the [`stm32f103xx`] crate so you'll have to add it
-//! to your Cargo.toml.
+//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
 //!
 //! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
 //!
 //! ```
-//! $ edit Cargo.toml && cat $_
+//! $ edit Cargo.toml && tail $_
 //! [dependencies.stm32f103xx]
 //! features = ["rt"]
-//! version = "0.8.0"
+//! version = "0.9.0"
 //! ```
 //!
 //! ---
@@ -29,9 +26,11 @@
 #![no_std]
 
 extern crate cortex_m;
+// extern crate cortex_m_rt; // included in the device crate
 extern crate cortex_m_semihosting;
 #[macro_use(exception, interrupt)]
 extern crate stm32f103xx;
+extern crate panic_abort; // panicking behavior
 
 use core::cell::RefCell;
 use core::fmt::Write;
@@ -41,11 +40,9 @@ use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m_semihosting::hio::{self, HStdout};
 use stm32f103xx::Interrupt;
 
-static HSTDOUT: Mutex<RefCell<Option<HStdout>>> =
-    Mutex::new(RefCell::new(None));
+static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
 
-static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> =
-    Mutex::new(RefCell::new(None));
+static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
 
 fn main() {
     let global_p = cortex_m::Peripherals::take().unwrap();

examples/hello.rs

@@ -8,6 +8,7 @@
 extern crate cortex_m;
 extern crate cortex_m_rt;
 extern crate cortex_m_semihosting;
+extern crate panic_abort; // panicking behavior
 
 use core::fmt::Write;