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@@ -43,7 +43,7 @@ Description: read only | |
This sysfs interface exposes the number of cores per chip | ||
present in the system. | ||
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What: /sys/devices/hv_24x7/interface/cpumask | ||
What: /sys/devices/hv_24x7/cpumask | ||
Date: July 2020 | ||
Contact: Linux on PowerPC Developer List <[email protected]> | ||
Description: read only | ||
|
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# | |
title: Freescale MXS GPIO controller | ||
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maintainers: | ||
- Shawn Guo <shawn.guo@linaro.org> | ||
- Shawn Guo <shawnguo@kernel.org> | ||
- Anson Huang <[email protected]> | ||
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description: | | ||
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@@ -9,6 +9,14 @@ title: PCIe RC controller on Intel Gateway SoCs | |
maintainers: | ||
- Dilip Kota <[email protected]> | ||
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select: | ||
properties: | ||
compatible: | ||
contains: | ||
const: intel,lgm-pcie | ||
required: | ||
- compatible | ||
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properties: | ||
compatible: | ||
items: | ||
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# | |
title: Freescale MXS PWM controller | ||
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maintainers: | ||
- Shawn Guo <shawn.guo@linaro.org> | ||
- Shawn Guo <shawnguo@kernel.org> | ||
- Anson Huang <[email protected]> | ||
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properties: | ||
|
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# | |
title: NXP i.MX Thermal Binding | ||
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maintainers: | ||
- Shawn Guo <shawn.guo@linaro.org> | ||
- Shawn Guo <shawnguo@kernel.org> | ||
- Anson Huang <[email protected]> | ||
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properties: | ||
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@@ -0,0 +1,60 @@ | ||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: SiFive Core Local Interruptor | ||
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maintainers: | ||
- Palmer Dabbelt <[email protected]> | ||
- Anup Patel <[email protected]> | ||
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description: | ||
SiFive (and other RISC-V) SOCs include an implementation of the SiFive | ||
Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor | ||
interrupts. It directly connects to the timer and inter-processor interrupt | ||
lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local | ||
interrupt controller is the parent interrupt controller for CLINT device. | ||
The clock frequency of CLINT is specified via "timebase-frequency" DT | ||
property of "/cpus" DT node. The "timebase-frequency" DT property is | ||
described in Documentation/devicetree/bindings/riscv/cpus.yaml | ||
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properties: | ||
compatible: | ||
items: | ||
- const: sifive,fu540-c000-clint | ||
- const: sifive,clint0 | ||
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description: | ||
Should be "sifive,<chip>-clint" and "sifive,clint<version>". | ||
Supported compatible strings are - | ||
"sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated | ||
onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive | ||
CLINT v0 IP block with no chip integration tweaks. | ||
Please refer to sifive-blocks-ip-versioning.txt for details | ||
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reg: | ||
maxItems: 1 | ||
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interrupts-extended: | ||
minItems: 1 | ||
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additionalProperties: false | ||
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required: | ||
- compatible | ||
- reg | ||
- interrupts-extended | ||
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examples: | ||
- | | ||
timer@2000000 { | ||
compatible = "sifive,fu540-c000-clint", "sifive,clint0"; | ||
interrupts-extended = <&cpu1intc 3 &cpu1intc 7 | ||
&cpu2intc 3 &cpu2intc 7 | ||
&cpu3intc 3 &cpu3intc 7 | ||
&cpu4intc 3 &cpu4intc 7>; | ||
reg = <0x2000000 0x10000>; | ||
}; | ||
... |
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