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Merge tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/…
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…linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - Support for the DA9063 as used on the HiFive Unmatched.

 - Support for relative extables, which puts us in line with other
   architectures and save some space in vmlinux.

 - A handful of kexec fixes/improvements, including the ability to run
   crash kernels from PCI-addressable memory on the HiFive Unmatched.

 - Support for the SBI SRST extension, which allows systems that do not
   have an explicit driver in Linux to reboot.

 - A handful of fixes and cleanups, including to the defconfigs and
   device trees.

* tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits)
  RISC-V: Use SBI SRST extension when available
  riscv: mm: fix wrong phys_ram_base value for RV64
  RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n
  riscv: head: remove useless __PAGE_ALIGNED_BSS and .balign
  riscv: errata: alternative: mark vendor_patch_func __initdata
  riscv: head: make secondary_start_common() static
  riscv: remove cpu_stop()
  riscv: try to allocate crashkern region from 32bit addressible memory
  riscv: use hart id instead of cpu id on machine_kexec
  riscv: Don't use va_pa_offset on kdump
  riscv: dts: sifive: fu540-c000: Fix PLIC node
  riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
  riscv: dts: sifive: Group tuples in register properties
  riscv: dts: sifive: Group tuples in interrupt properties
  riscv: dts: microchip: mpfs: Group tuples in interrupt properties
  riscv: dts: microchip: mpfs: Fix clock controller node
  riscv: dts: microchip: mpfs: Fix reference clock node
  riscv: dts: microchip: mpfs: Fix PLIC node
  riscv: dts: microchip: mpfs: Drop empty chosen node
  riscv: dts: canaan: Group tuples in interrupt properties
  ...
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@torvalds
torvalds committed Jan 19, 2022
2 parents fd6f57b + b579dfe commit f1b744f
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Showing 42 changed files with 512 additions and 392 deletions.
4 changes: 3 additions & 1 deletion arch/riscv/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ config RISCV
def_bool y
select ARCH_CLOCKSOURCE_INIT
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DEBUG_VIRTUAL if MMU
Expand Down Expand Up @@ -75,6 +76,7 @@ config RISCV
select HAVE_ARCH_SECCOMP_FILTER
select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
select HAVE_ARCH_THREAD_STRUCT_WHITELIST
select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
select HAVE_ASM_MODVERSIONS
Expand Down Expand Up @@ -279,7 +281,7 @@ choice
depends on 32BIT
bool "1GiB"
config MAXPHYSMEM_2GB
depends on 64BIT && CMODEL_MEDLOW
depends on 64BIT
bool "2GiB"
config MAXPHYSMEM_128GB
depends on 64BIT && CMODEL_MEDANY
Expand Down
23 changes: 12 additions & 11 deletions arch/riscv/boot/dts/canaan/k210.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -103,8 +103,8 @@
clint0: timer@2000000 {
compatible = "canaan,k210-clint", "sifive,clint0";
reg = <0x2000000 0xC000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
};

plic0: interrupt-controller@c000000 {
Expand All @@ -113,7 +113,7 @@
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
riscv,ndev = <65>;
};

Expand All @@ -130,18 +130,19 @@
compatible = "canaan,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
interrupts = <34 35 36 37 38 39 40 41
42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65>;
interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
<41>, <42>, <43>, <44>, <45>, <46>, <47>,
<48>, <49>, <50>, <51>, <52>, <53>, <54>,
<55>, <56>, <57>, <58>, <59>, <60>, <61>,
<62>, <63>, <64>, <65>;
gpio-controller;
ngpios = <32>;
};

dmac0: dma-controller@50000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27 28 29 30 31 32>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
clock-names = "core-clk", "cfgr-clk";
Expand Down Expand Up @@ -316,7 +317,7 @@
timer0: timer@502d0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14 15>;
interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
Expand All @@ -326,7 +327,7 @@
timer1: timer@502e0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16 17>;
interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
Expand All @@ -336,7 +337,7 @@
timer2: timer@502f0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18 19>;
interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
Expand Down
2 changes: 1 addition & 1 deletion arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -199,7 +199,7 @@
};

&spi3 {
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
Expand Down
2 changes: 1 addition & 1 deletion arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -201,7 +201,7 @@
};

&spi3 {
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
Expand Down
2 changes: 1 addition & 1 deletion arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -209,7 +209,7 @@
};

&spi3 {
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
Expand Down
2 changes: 1 addition & 1 deletion arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,7 @@
};

&spi3 {
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
Expand Down
4 changes: 4 additions & 0 deletions arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,10 @@
};
};

&refclk {
clock-frequency = <600000000>;
};

&serial0 {
status = "okay";
};
Expand Down
60 changes: 24 additions & 36 deletions arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,6 @@
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";

chosen {
};

cpus {
#address-cells = <1>;
#size-cells = <0>;
Expand Down Expand Up @@ -142,6 +139,11 @@
};
};

refclk: msspllclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};

soc {
#address-cells = <2>;
#size-cells = <2>;
Expand All @@ -156,62 +158,48 @@
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1 2 3>;
interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};

clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>;
};

plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <186>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11
&cpu1_intc 11 &cpu1_intc 9
&cpu2_intc 11 &cpu2_intc 9
&cpu3_intc 11 &cpu3_intc 9
&cpu4_intc 11 &cpu4_intc 9>;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
riscv,ndev = <186>;
};

dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <23 24 25 26 27 28 29 30>;
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
<30>;
#dma-cells = <1>;
};

refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
clock-output-names = "msspllclk";
};

clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;
clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
"mac0", "mac1", "mmc", "timer", /* 4-7 */
"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
"i2c1", "can0", "can1", "usb", /* 16-19 */
"rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
"gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
};

serial0: serial@20000000 {
Expand Down Expand Up @@ -267,7 +255,7 @@
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88 89>;
interrupts = <88>, <89>;
clocks = <&clkcfg 6>;
max-frequency = <200000000>;
status = "disabled";
Expand All @@ -277,7 +265,7 @@
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
interrupt-parent = <&plic>;
interrupts = <64 65 66 67>;
interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 4>, <&clkcfg 2>;
clock-names = "pclk", "hclk";
Expand All @@ -290,7 +278,7 @@
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
interrupt-parent = <&plic>;
interrupts = <70 71 72 73>;
interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 5>, <&clkcfg 2>;
status = "disabled";
Expand Down
40 changes: 21 additions & 19 deletions arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -137,20 +137,21 @@
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <53>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <
&cpu0_intc 0xffffffff
&cpu1_intc 0xffffffff &cpu1_intc 9
&cpu2_intc 0xffffffff &cpu2_intc 9
&cpu3_intc 0xffffffff &cpu3_intc 9
&cpu4_intc 0xffffffff &cpu4_intc 9>;
interrupts-extended =
<&cpu0_intc 0xffffffff>,
<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
riscv,ndev = <53>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
Expand All @@ -170,7 +171,8 @@
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic0>;
interrupts = <23 24 25 26 27 28 29 30>;
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
<30>;
#dma-cells = <1>;
};
uart1: serial@10011000 {
Expand All @@ -195,8 +197,8 @@
};
qspi0: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
reg = <0x0 0x10040000 0x0 0x1000
0x0 0x20000000 0x0 0x10000000>;
reg = <0x0 0x10040000 0x0 0x1000>,
<0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <51>;
clocks = <&prci PRCI_CLK_TLCLK>;
Expand All @@ -206,8 +208,8 @@
};
qspi1: spi@10041000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
reg = <0x0 0x10041000 0x0 0x1000
0x0 0x30000000 0x0 0x10000000>;
reg = <0x0 0x10041000 0x0 0x1000>,
<0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
clocks = <&prci PRCI_CLK_TLCLK>;
Expand All @@ -229,8 +231,8 @@
compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>;
interrupts = <53>;
reg = <0x0 0x10090000 0x0 0x2000
0x0 0x100a0000 0x0 0x1000>;
reg = <0x0 0x10090000 0x0 0x2000>,
<0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
Expand All @@ -243,7 +245,7 @@
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <42 43 44 45>;
interrupts = <42>, <43>, <44>, <45>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
Expand All @@ -252,7 +254,7 @@
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <46 47 48 49>;
interrupts = <46>, <47>, <48>, <49>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
Expand All @@ -265,7 +267,7 @@
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
interrupts = <1 2 3>;
interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
Expand Down
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