Added in 40GbE yellow block reset and removed ila

The 40GbE yellow block reset has been added. It will only reset the application layer. The FIFO write/read is now gated with the reset for added protection. The hard-coded ila has been removed. It has never really been used.
ska-sa · Nov 14, 2017 · 21093e6 · 21093e6
1 parent 2dabf78
commit 21093e6
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Showing 87 changed files with 40 additions and 576,067 deletions.
diff --git a/jasper_library/hdl_sources/forty_gbe/SKA_40GBE_MAC/ska_fge_rx.vhd b/jasper_library/hdl_sources/forty_gbe/SKA_40GBE_MAC/ska_fge_rx.vhd
@@ -997,9 +997,10 @@ begin
     packet_fifo_wr_data(261) <= rx_bad;
     packet_fifo_wr_data(262) <= rx_over;
 
+    --AI: Alway deassert FIFO write when reset is asserted
     packet_fifo_wr_en <= '1' when
     ((app_dvld_z1  = '1')and
-    (current_app_state = APP_RUN)) else '0';
+    (current_app_state = APP_RUN) and (app_rst = '0')) else '0';
 
     ska_rx_packet_fifo_0 : ska_rx_packet_fifo
     port map(
@@ -1013,8 +1014,9 @@ begin
         full        => open,
         empty       => packet_fifo_empty,
         prog_full   => packet_fifo_almost_full);
-
-    packet_fifo_rd_en <= app_rx_ack;
+
+    --AI: Alway deassert FIFO read when reset is asserted 
+    packet_fifo_rd_en <= app_rx_ack and (not app_rst);
 
     app_rx_valid        <= packet_fifo_rd_data(259 downto 256) when (packet_fifo_empty = '0') else (others => '0');
     app_rx_end_of_frame <= packet_fifo_rd_data(260);
@@ -1023,7 +1025,8 @@ begin
     app_rx_data         <= packet_fifo_rd_data(255 downto 0);
 
     ctrl_fifo_wr_data <= app_source_port & app_source_ip;
-    ctrl_fifo_wr_en   <= '1' when ((app_dvld = '1')and(first_word = '1')and(current_app_state = APP_RUN)) else '0';
+    --AI: Alway deassert FIFO write when reset is asserted
+    ctrl_fifo_wr_en   <= '1' when ((app_dvld = '1')and(first_word = '1')and(current_app_state = APP_RUN) and (app_rst = '0')) else '0';
     txctrl_fifo_wr_data <= destination_port & destination_ip;
     --txctrl_fifo_wr_en   <= '1' when ((app_dvld = '1')and(first_word = '1')and(current_app_state = APP_RUN)) else '0';
 
@@ -1039,8 +1042,9 @@ begin
         full        => open,
         empty       => ctrl_fifo_empty,
         prog_full   => ctrl_fifo_almost_full);
-
-    ctrl_fifo_rd_en <= app_rx_ack and  packet_fifo_rd_data(260) and packet_fifo_rd_data(256);
+
+    --AI: Alway deassert FIFO read when reset is asserted
+    ctrl_fifo_rd_en <= app_rx_ack and  packet_fifo_rd_data(260) and packet_fifo_rd_data(256) and (not app_rst);
 
     app_rx_source_ip   <= ctrl_fifo_rd_data(31 downto 0);
     app_rx_source_port <= ctrl_fifo_rd_data(47 downto 32);

diff --git a/jasper_library/hdl_sources/forty_gbe/SKA_40GBE_MAC/ska_fge_tx.vhd b/jasper_library/hdl_sources/forty_gbe/SKA_40GBE_MAC/ska_fge_tx.vhd
@@ -635,7 +635,8 @@ begin
     --app_tx_data_din <= app_tx_valid_z1 & app_tx_data_z1;
     app_tx_data_din <= app_tx_end_of_frame_z1 & "000" & app_tx_valid_z1 & app_tx_data_z1;
 
-    app_tx_data_wrreq <= app_tx_any_valid and (not app_tx_data_full);
+    --AI: Deassert write when FIFO full and reset asserted
+    app_tx_data_wrreq <= app_tx_any_valid and (not app_tx_data_full) and (not app_rst);
 
     gen_app_tx_data_wrreq_latched : process(app_rst, app_clk)
     begin
@@ -661,8 +662,9 @@ begin
         overflow    => app_tx_data_overflow,
         empty       => app_tx_data_empty,
         prog_full   => app_tx_data_afull);
-
-    app_tx_data_rdreq <= app_tx_data_rd and (not app_tx_data_empty);
+
+    --AI: Deassert read when FIFO empty and reset asserted
+    app_tx_data_rdreq <= app_tx_data_rd and (not app_tx_data_empty) and (not app_rst);
 
     payload0 <= app_tx_data_dout(63 downto 0);
     payload1 <= app_tx_data_dout(127 downto 64);
@@ -684,7 +686,8 @@ begin
     end process;
 
     -- CONTROL FIFO TO MOVE IP, PORT AND PACKET COUNT TO MAC CLOCK DOMAIN
-    app_tx_ctrl_wrreq <= app_tx_ctrl_fifo_en and (not app_tx_ctrl_full);
+    -- AI: Deassert write when FIFO full and reset asserted
+    app_tx_ctrl_wrreq <= app_tx_ctrl_fifo_en and (not app_tx_ctrl_full) and (not app_rst);
 
     app_tx_ctrl_din(31 downto 0) <= app_tx_dest_ip_z1;
     app_tx_ctrl_din(47 downto 32) <= app_tx_dest_port_z1;
@@ -717,7 +720,8 @@ begin
         empty       => app_tx_ctrl_empty,
         prog_full   => app_tx_ctrl_afull);
 
-    app_tx_ctrl_rdreq <= app_tx_ctrl_rd and (not app_tx_ctrl_empty);
+   --AI: Deassert read when FIFO empty and reset asserted
+    app_tx_ctrl_rdreq <= app_tx_ctrl_rd and (not app_tx_ctrl_empty) and (not app_rst);
 
 	gen_app_tx_afull : process(app_clk)
 	begin
@@ -1186,7 +1190,11 @@ begin
 
             end case;
 
-            --AI: 2/11/2017: Allows read state machine to synchronise with TX Data Packet FIFO 
+            --AI: 2/11/2017: Allows read state machine to synchronise with TX Data Packet FIFO
+            --Only providing for GEN_PAYLOAD_FINISH_4 now, SKA-SA will always send 256 bits per
+            --a transaction (4 x 64 bits words) and hence, tx_size will always end at 0x4. Provision
+            --has been made for 4 data valids, but in reality all 4 data valids will be asserted at once. This
+            --could of been coded with 1 data valid.
             if (payload_end_of_frame = '1' and  eof_flag_activate = '0') then
                 current_tx_packet_state <= GEN_PAYLOAD_FINISH_4;
                 eof_flag_activate <= '1';

diff --git a/jasper_library/hdl_sources/forty_gbe/forty_gbe.vhd b/jasper_library/hdl_sources/forty_gbe/forty_gbe.vhd
@@ -48,7 +48,7 @@ entity forty_gbe is
         user_clk_o : out std_logic;
         user_rst_o : out std_logic;
         hmc_rst_o : out std_logic;
-        hmc_clk_o : out std_logic;
+        hmc_clk_o : out std_logic; 
 
         FPGA_RESET_N       : in std_logic;
         FPGA_REFCLK_BUF0_P : in std_logic;
@@ -224,7 +224,8 @@ entity forty_gbe is
 
         EMCCLK_FIX : out std_logic;
         GND        : out std_logic_vector(15 downto 0);
-
+
+        forty_gbe_rst             : in  std_logic;
         forty_gbe_tx_valid        : in  std_logic_vector(3 downto 0);
         forty_gbe_tx_end_of_frame : in  std_logic;
         forty_gbe_tx_data         : in  std_logic_vector(255 downto 0);
@@ -774,6 +775,7 @@ architecture arch_forty_gbe of forty_gbe is
     attribute ASYNC_REG of sync_emcclk_fpga_rst3: signal is "TRUE";                
     signal user_rst : std_logic;
     signal user_fpga_rst : std_logic;
+    signal user_40gbe_rst : std_logic;
     signal sys_clk : std_logic;
     signal sys_rst : std_logic; 
     signal sys_rst_i : std_logic;
@@ -2180,15 +2182,18 @@ begin
     --AI End: Added fortygbe config interface
 
     --AI: Allows 40GbE configuration using the system clock and normal 40GbE data interfacing using the user clock
-    fpga_user_sysclk_bufgmux_ctrl : BUFGMUX_CTRL
-    port map (
-        I0 => sys_clk,
-        I1 => user_clk,
-        S  => select_forty_gbe_data_sel,
-        O  => forty_gb_eth_clk);  
+    --fpga_user_sysclk_bufgmux_ctrl : BUFGMUX_CTRL
+    --port map (
+    --    I0 => sys_clk,
+    --    I1 => user_clk,
+    --    S  => select_forty_gbe_data_sel,
+    --    O  => forty_gb_eth_clk);  
 
     --AI: Allows 40GbE configuration using the system reset and normal 40GbE data interfacing using the user reset    
-    forty_gb_eth_rst <= sys_rst when (select_forty_gbe_data_sel  = '0') else user_rst; 
+    --forty_gb_eth_rst <= sys_rst when (select_forty_gbe_data_sel  = '0') else user_rst; 
+
+    --AI: 40GbE Yellow Block Reset  or'd with user_rst
+    user_40gbe_rst <= forty_gbe_rst or user_rst;
 
     -- WISHBONE SLAVE 10 - 40GBE MAC 0
     ska_forty_gb_eth_0 : ska_forty_gb_eth
@@ -2204,7 +2209,7 @@ begin
         RX_CRC_CHK_ENABLE => RX_CRC_CHK_ENABLE)
     port map(
         clk => user_clk, --forty_gb_eth_clk,
-        rst => user_rst, --forty_gb_eth_rst,
+        rst => user_40gbe_rst,--user_rst, --forty_gb_eth_rst,
         tx_valid            => xlgmii_tx_valid,
         tx_end_of_frame     => xlgmii_tx_end_of_frame,
         tx_data             => xlgmii_tx_data,