Added changes to bus_dual_port_ram_init.m to accommodate Ultra RAM.

Added platfor_devices to assist in platform lookup (to see if Ultra RAM supported).

casper_library/bus_dual_port_ram_init.m

@@ -96,7 +96,7 @@ function bus_dual_port_ram_init(blk, varargin)
   enb_implementation        = get_var('enb_implementation', 'defaults', defaults, varargin{:});
 
   delete_lines(blk);
-
+  
   %default state, do nothing 
   if (n_bits(1) == 0),
     clean_blocks(blk);
@@ -105,6 +105,34 @@ function bus_dual_port_ram_init(blk, varargin)
     return;
   end
 
+    %get hardware platform from XSG block
+  try
+    xsg_blk = find_system(bdroot, 'SearchDepth', 1,'FollowLinks','on','LookUnderMasks','all','Tag','xps:xsg');
+    hw_sys = xps_get_hw_plat(get_param(xsg_blk{1},'hw_sys'));
+
+    platform_devices = readtable('docs/platform_devices.csv','ReadVariableNames',false);
+
+    for idx = 1:height(platform_devices),
+        if strcmp(hw_sys, platform_devices{idx,1})
+            fpga_family = platform_devices{idx,3};
+        end
+    end %end for device_table
+
+    if ~strcmp(fpga_family, 'UltraScalePlus')
+      if strcmp(mem_type,'Ultra RAM')
+        clog('Ultra RAM selected for a non-UltraScale+ device. This can result in error.', {log_group});
+        warning('bus_dual_port_ram_init: Ultra RAM selected for a non-UltraScale+ device. This can result in error.');
+        warndlg('bus_dual_port_ram_init: Ultra RAM selected for a non-UltraScale+ device. This can result in error.','Warning');
+      end
+    end
+
+  catch,
+    clog('Could not find hardware platform - is there an XSG block in this model? Defaulting platform to ROACH.', {log_group});
+    warning('bus_dual_port_ram_init: Could not find hardware platform - is there an XSG block in this model? Defaulting platform to ROACH.');
+    fpga_family = 'Virtex';
+    hw_sys = 'ROACH';
+  end %try/catch
+
   [riv, civ]  = size(init_vector);
   [rnb, cnb]  = size(n_bits);
   [rbp, cbp]  = size(bin_pts);
@@ -404,7 +432,7 @@ function bus_dual_port_ram_init(blk, varargin)
     add_line(blk, 'concata/1', 'prom_wea/1'); 
     ypos_tmp  = ypos_tmp + yinc + bus_expand_d*replication/2;
 
-    if strcmp(mem_type, 'Block RAM'),
+    if strcmp(mem_type, 'Block RAM')||strcmp(mem_type, 'Ultra RAM'),
       ypos_tmp  = ypos_tmp + yinc + bus_expand_d*ctiv; %dinb
       ypos_tmp  = ypos_tmp + bus_expand_d*replication/2;
       reuse_block(blk, 'prom_web', 'xbsIndex_r4/ROM', ...
@@ -480,7 +508,7 @@ function bus_dual_port_ram_init(blk, varargin)
     add_line(blk, 'prom_wea/1', 'debus_wea/1'); 
     ypos_tmp  = ypos_tmp + yinc + bus_expand_d*replication/2;
 
-    if strcmp(mem_type, 'Block RAM'),
+    if strcmp(mem_type, 'Block RAM')||strcmp(mem_type, 'Ultra RAM'),
       ypos_tmp  = ypos_tmp + yinc + bus_expand_d*ctiv; %dinb
       ypos_tmp  = ypos_tmp + bus_expand_d*replication/2;
       reuse_block(blk, 'debus_web', 'casper_library_flow_control/bus_expand', ...
@@ -593,7 +621,7 @@ function bus_dual_port_ram_init(blk, varargin)
     end % if banks
     ypos_tmp  = ypos_tmp + yinc + bus_expand_d*replication/2;
 
-    if strcmp(mem_type, 'Block RAM'),
+    if strcmp(mem_type, 'Block RAM')||strcmp(mem_type, 'Ultra RAM'),
       % delay dinb
       if strcmp(dinb_implementation, 'core'), reg_retiming = 'off';
       else, reg_retiming = 'on';
@@ -737,7 +765,7 @@ function bus_dual_port_ram_init(blk, varargin)
     %space for addrb slice
 %    ypos_tmp  = ypos_tmp + yinc + slice_d;
 
-    if strcmp(mem_type, 'Block RAM'),
+    if strcmp(mem_type, 'Block RAM')||strcmp(mem_type, 'Ultra RAM'),
       % debus dinb
       ypos_tmp        = ypos_tmp + bus_expand_d*ctiv/2;
       reuse_block(blk, ['debus_dinb',num2str(bank_index)], 'casper_library_flow_control/bus_expand', ...
@@ -860,7 +888,7 @@ function bus_dual_port_ram_init(blk, varargin)
       add_line(blk, ['debus_addrb', num2str(bank_index), '/', num2str(rep_index)], [bram_name, '/4']);
 
       port_index = 4;
-      if strcmp(mem_type, 'Block RAM'),
+      if strcmp(mem_type, 'Block RAM')||strcmp(mem_type, 'Ultra RAM'),
         add_line(blk, ['debus_dinb', num2str(bank_index), '/', num2str(bram_index)], [bram_name, '/5']);
         add_line(blk, ['debus_web', num2str(bank_index), '/', num2str(rep_index)], [bram_name, '/6']);
         port_index = 6;

casper_library/casper_library_bus_initialize.m

@@ -337,7 +337,7 @@ function casper_library_bus_initialize()
 	set_param(blk, ...
 		'Name', sprintf('casper_library_bus'), ...
 		'LibraryType', sprintf('BlockLibrary'), ...
-		'Lock', sprintf('off'), ...
+		'Lock', sprintf('on'), ...
 		'PreSaveFcn', sprintf('mdl2m(gcs, ''library'', ''on'');'), ...
 		'SolverName', sprintf('ode45'), ...
 		'SolverMode', sprintf('SingleTasking'), ...
@@ -786,8 +786,7 @@ function bus_dual_port_ram_mask(blk)
 		'MaskType', sprintf('bus_dual_port_ram'), ...
 		'MaskDescription', sprintf('RAM for a bus allowing fanout control'), ...
 		'MaskPromptString', sprintf('data word bit widths|data word binary points|initial value vector|limit fanout to ?|memory type|memory optimization|a asynchronous|b asynchronous|b_to_a ratio bits|misc support|bram latency|input register latency|addra input register|addra register implementation|dina input register|dina register implementation|wea input register|wea register implementation|ena input register|ena register implementation|addrb input register|addrb register implementation|dinb input register|dinb register implementation|web input register|web register implementation|enb input register|enb register implementation'), ...
-		'MaskStyleString', sprintf('edit,edit,edit,edit,popup(Distributed memory|Block RAM),popup(Area|Speed),checkbox,checkbox,edit,checkbox,edit,edit,checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral)'), ...
-		'MaskTabNameString', sprintf('basic,basic,basic,basic,basic,basic,basic,basic,basic,basic,latency,latency,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation,implementation'), ...
+		'MaskStyleString', sprintf('edit,edit,edit,edit,popup(Distributed memory|Block RAM|Ultra RAM),popup(Area|Speed),checkbox,checkbox,edit,checkbox,edit,edit,checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral),checkbox,popup(core|behavioral)'), ...
 		'MaskCallbackString', sprintf('|||||||||||||||||||||||||||'), ...
 		'MaskEnableString', sprintf('on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on'), ...
 		'MaskVisibilityString', sprintf('on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on'), ...

docs/platform_devices.csv

@@ -0,0 +1,22 @@
+Platform,Device,Family,Ultra RAM
+ADM_PCIE_9H7,xcvu37p,UltraScalePlus,Yes
+AU280,xcu280,UltraScalePlus,Yes
+AU50,xcu50,UltraScalePlus,Yes
+CASIA_K7,xc7k325t,Kintex7,No
+CASIA_K7_21CMA,xc7k325t,Kintex7,No
+HTG9200,xcvu13p,UltraScalePlus,Yes
+HTG940,xcvu13p,UltraScalePlus,Yes
+htg_zrf16,xczu49dr,UltraScalePlus,Yes
+MX175,xc7vx690t,Virtex7,No
+RED_PITAYA_10,xc7z010,Zynq,No
+rfsoc2x2,xczu28dr,Zynq UltraScalePlus,Yes
+rfsoc4x2,xczu48dr,Zynq UltraScalePlus,Yes
+SKARAB,xc7vx690t,Virtex7,No
+SNAP,xc7k160t,Kintex7,No
+SNAP2_v1,xcku115,Kintex UltraScale,No
+VCU118,xcvu9p,Virtex UltraScalePlus,Yes
+VCU128,xcvu37p,Virtex UltraScalePlus,Yes
+ZCU111,xczu28dr,Zynq UltraScalePlus,Yes
+ZCU208,xczu48dr,Zynq UltraScalePlus,Yes
+ZCU216,xczu49dr,Zynq UltraScalePlus,Yes
+ZRF16_49DR,xczu49dr,Zynq UltraScalePlus,Yes