update zcu216 platform file

.gitignore

@@ -32,4 +32,7 @@ xps_base/XPS_ROACH2_base/system.xmp.updated
 vivado_pid*.str
 
 # ignore docs build directory
-docs/_build/
+docs/_build/
+
+src/*
+workspace/*

casper_library/casper_library_bus_initialize.m

@@ -340,7 +340,7 @@ function casper_library_bus_initialize()
 		'Lock', sprintf('on'), ...
 		'PreSaveFcn', sprintf('mdl2m(gcs, ''library'', ''on'');'), ...
 		'SolverName', sprintf('ode45'), ...
-		'SolverMode', sprintf('MultiTasking'), ...
+		'SolverMode', sprintf('SingleTasking'), ...
 		'StartTime', sprintf('0.0'), ...
 		'StopTime', sprintf('10.0'));
 	filename = save_system(mdl,[getenv('MLIB_DEVEL_PATH'), '/casper_library/', 'casper_library_bus', '.slx']);

jasper_library/.gitignore

@@ -1,4 +1,5 @@
 test_models/*
 .Xil
-!test_models/*.slx
+test_models/*.slx
 *.pyc
+

jasper_library/hdl_sources/infrastructure/zcu111.tcl

@@ -44,7 +44,6 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 set list_projs [get_projects -quiet]
 if { $list_projs eq "" } {
    create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
-   set_property BOARD_PART xilinx.com:zcu111:part0:1.2 [current_project]
 }
 
 
@@ -203,9 +202,21 @@ proc create_root_design { parentCell } {
    CONFIG.PROTOCOL {AXI4LITE} \
    ] $M_AXI
 
+  set RFDC_M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 RFDC_M_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.DATA_WIDTH {32} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4} \
+   ] $RFDC_M_AXI
+
 
   # Create ports
   set axil_clk [ create_bd_port -dir O -type clk axil_clk ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {RFDC_M_AXI} \
+ ] $axil_clk
   set axil_rst [ create_bd_port -dir O -from 0 -to 0 -type rst axil_rst ]
   set axil_rst_n [ create_bd_port -dir O -from 0 -to 0 -type rst axil_rst_n ]
 
@@ -215,7 +226,7 @@ proc create_root_design { parentCell } {
   # Create instance: ps8_0_axi_periph, and set properties
   set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
   set_property -dict [ list \
-   CONFIG.NUM_MI {1} \
+   CONFIG.NUM_MI {2} \
  ] $ps8_0_axi_periph
 
   # Create instance: zynq_ultra_ps_e_0, and set properties
@@ -885,16 +896,18 @@ proc create_root_design { parentCell } {
 
   # Create interface connections
   connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_ports M_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_ports RFDC_M_AXI] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
   connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
 
   # Create port connections
-  connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports axil_rst_n] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN]
+  connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports axil_rst_n] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN]
   connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_ports axil_rst] [get_bd_pins proc_sys_reset_0/peripheral_reset]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_ports axil_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_ports axil_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
   connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
 
   # Create address segments
   create_bd_addr_seg -range 0x00010000 -offset 0xA0000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs M_AXI/Reg] SEG_M_AXI_Reg
+  create_bd_addr_seg -range 0x00010000 -offset 0xA0010000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs RFDC_M_AXI/Reg] SEG_RFDC_M_AXI_Reg
 
 
   # Restore current instance

jasper_library/hdl_sources/infrastructure/zcu111_infrastructure.v

@@ -1,20 +1,19 @@
-module zcu111_infrastructure #(
-        parameter MULTIPLY = 1,
-        parameter DIVIDE   = 1,
-        parameter DIVCLK   = 1
-    ) (
-
-        input clk_100_n,
-	input clk_100_p,
 
-	output sys_clk,
-	output sys_clk90,
-	output sys_clk180,
-	output sys_clk270,
+module zcu111_infrastructure #(
+  parameter MULTIPLY = 1,
+  parameter DIVIDE   = 1,
+  parameter DIVCLK   = 1
+) (
+  input clk_100_n,
+  input clk_100_p,
 
-        output sys_clk_rst
+  output sys_clk,
+  output sys_clk90,
+  output sys_clk180,
+  output sys_clk270,
 
-    );
+  output sys_clk_rst
+);
 
     wire clk_100;
     wire user_clk_mmcm_fb;

jasper_library/platforms/zcu111.yaml

@@ -13,7 +13,24 @@ sources: []
 constraints: []
 
 rfdc:
-  gen: 2
+  # gen3 devices can internally route their input refclk or the output of the RFPLL
+  # as the sample clock for adjacent tiles. See PG269. For such configurations,
+  # tile 225 is the preferred tile when available. The zcu216/208 eval boards only
+  # have the sample clock connected to tile 255.
+  #
+  # For gen1 and gen2 devices the `adc_clk_src` is the same as the tile index
+  tile224:
+    has_adc_clk: True
+    adc_clk_src: 1
+  tile225:
+    has_adc_clk: True
+    adc_clk_src: 2
+  tile226:
+    has_adc_clk: True
+    adc_clk_src: 3
+  tile227:
+    has_adc_clk: True
+    adc_clk_src: 4
 
 onehundredgbe:
   # does the freq matter much?
@@ -26,6 +43,7 @@ provides:
   - axil_clk # keep this? come from pl_clk? or use clk100?
 # TODO: does name matter? Jack's 100G block should list what the provides therefore this matters
   - sfp4x25
+  - sysref_in
 
 pins:
   clk_100_p:
@@ -35,6 +53,12 @@ pins:
     iostd: LVDS
     loc: AN15
 
+# NOTE: most of the IO constraints and clocking constraints are taken care of by
+# the RFDC IP itself. Vivado has that baked into the output products of teh IP
+# core. The only necessary pins below are the fabirc clocking related to
+# multi-tile sync Adding additional pins and constraints would not hurt anything
+# but provide more transparent less 'hand-wavy'
+
 # RFDC clocking
   # `SYSREF_P/N_228` on bank 228
   # constraints determined by rfdc ip, iostandard and loc not set by user

jasper_library/platforms/zcu216.yaml

@@ -12,9 +12,25 @@ mmbus_address_alignment: 4
 sources: []
 constraints: []
 
-# potential idea for help in rfdc capability support (e.g., clock distribution?)
 rfdc:
-  gen: 3
+  # gen3 devices can internally route their input refclk or the output of the RFPLL
+  # as the sample clock for adjacent tiles. See PG269. For such configurations,
+  # tile 225 is the preferred tile when available. The zcu216/208 eval boards only
+  # have the sample clock connected to tile 255.
+  #
+  # For gen1 and gen2 devices the `adc_clk_src` is the same as the tile index
+  tile224:
+    has_adc_clk: False
+    adc_clk_src: 1
+  tile225:
+    has_adc_clk: True
+    adc_clk_src: 1
+  tile226:
+    has_adc_clk: True
+    adc_clk_src: 1
+  tile227:
+    has_adc_clk: False
+    adc_clk_src: 1
 
 onehundredgbe:
   # does the freq matter much?
@@ -26,7 +42,8 @@ onehundredgbe:
 provides:
   - adc_clk
   - axil_clk # TODO: keep this? come from pl_clk on mpsoc? Or use clk100?
-  - sfp4x25  
+  - sfp4x25  # TODO this isn't the right name
+  - sysref_in
 
 pins:
   clk_100_p:
@@ -42,10 +59,11 @@ pins:
     iostd: LVDS_25
     loc: A12
 
-# So I think the idea is that we don't actually have to assign anything, Vivado
-# knows all...
-# But it may be a good idea to still put them and either A) see what happens, or
-# B) just make a note for the present/future developers
+# NOTE: most of the IO constraints and clocking constraints are taken care of by
+# the RFDC IP itself. Vivado has that baked into the output products of teh IP
+# core. The only necessary pins below are the fabirc clocking related to
+# multi-tile sync Adding additional pins and constraints would not hurt anything
+# but provide more transparent less 'hand-wavy'
 # RFDC clocking
 
   # `SYSREF_P/N_228` on bank 228

jasper_library/yellow_blocks/zcu111.py

@@ -21,26 +21,48 @@ def modify_top(self,top):
         inst.add_port('axil_rst',   'axil_rst')
         inst.add_port('axil_rst_n', 'axil_rst_n')
 
-        inst.add_port('M_AXI_araddr', 'M_AXI_araddr', width=32)
-        inst.add_port('M_AXI_arprot', 'M_AXI_arprot', width=3)
+        # sys_block master interface
+        inst.add_port('M_AXI_araddr',  'M_AXI_araddr', width=32)
+        inst.add_port('M_AXI_arprot',  'M_AXI_arprot', width=3)
         inst.add_port('M_AXI_arready', 'M_AXI_arready')
         inst.add_port('M_AXI_arvalid', 'M_AXI_arvalid')
-        inst.add_port('M_AXI_awaddr', 'M_AXI_awaddr', width=32)
-        inst.add_port('M_AXI_awprot', 'M_AXI_awprot', width=3)
+        inst.add_port('M_AXI_awaddr',  'M_AXI_awaddr', width=32)
+        inst.add_port('M_AXI_awprot',  'M_AXI_awprot', width=3)
         inst.add_port('M_AXI_awready', 'M_AXI_awready')
         inst.add_port('M_AXI_awvalid', 'M_AXI_awvalid')
-        inst.add_port('M_AXI_bready', 'M_AXI_bready')
-        inst.add_port('M_AXI_bresp', 'M_AXI_bresp', width=2)
-        inst.add_port('M_AXI_bvalid', 'M_AXI_bvalid')
-        inst.add_port('M_AXI_rdata', 'M_AXI_rdata', width=32)
-        inst.add_port('M_AXI_rready', 'M_AXI_rready')
-        inst.add_port('M_AXI_rresp', 'M_AXI_rresp', width=2)
-        inst.add_port('M_AXI_rvalid', 'M_AXI_rvalid')
-        inst.add_port('M_AXI_wdata', 'M_AXI_wdata', width=32)
-        inst.add_port('M_AXI_wready', 'M_AXI_wready')
-        inst.add_port('M_AXI_wstrb', 'M_AXI_wstrb', width=4)
-        inst.add_port('M_AXI_wvalid', 'M_AXI_wvalid')
-
+        inst.add_port('M_AXI_bready',  'M_AXI_bready')
+        inst.add_port('M_AXI_bresp',   'M_AXI_bresp', width=2)
+        inst.add_port('M_AXI_bvalid',  'M_AXI_bvalid')
+        inst.add_port('M_AXI_rdata',   'M_AXI_rdata', width=32)
+        inst.add_port('M_AXI_rready',  'M_AXI_rready')
+        inst.add_port('M_AXI_rresp',   'M_AXI_rresp', width=2)
+        inst.add_port('M_AXI_rvalid',  'M_AXI_rvalid')
+        inst.add_port('M_AXI_wdata',   'M_AXI_wdata', width=32)
+        inst.add_port('M_AXI_wready',  'M_AXI_wready')
+        inst.add_port('M_AXI_wstrb',   'M_AXI_wstrb', width=4)
+        inst.add_port('M_AXI_wvalid',  'M_AXI_wvalid')
+
+        # RFDC master interface
+        inst.add_port('RFDC_M_AXI_araddr',  'RFDC_M_AXI_araddr', width=32)
+        inst.add_port('RFDC_M_AXI_arprot',  'RFDC_M_AXI_arprot', width=3)
+        inst.add_port('RFDC_M_AXI_arready', 'RFDC_M_AXI_arready')
+        inst.add_port('RFDC_M_AXI_arvalid', 'RFDC_M_AXI_arvalid')
+        inst.add_port('RFDC_M_AXI_awaddr',  'RFDC_M_AXI_awaddr', width=32)
+        inst.add_port('RFDC_M_AXI_awprot',  'RFDC_M_AXI_awprot', width=3)
+        inst.add_port('RFDC_M_AXI_awready', 'RFDC_M_AXI_awready')
+        inst.add_port('RFDC_M_AXI_awvalid', 'RFDC_M_AXI_awvalid')
+        inst.add_port('RFDC_M_AXI_bready',  'RFDC_M_AXI_bready')
+        inst.add_port('RFDC_M_AXI_bresp',   'RFDC_M_AXI_bresp', width=2)
+        inst.add_port('RFDC_M_AXI_bvalid',  'RFDC_M_AXI_bvalid')
+        inst.add_port('RFDC_M_AXI_rdata',   'RFDC_M_AXI_rdata', width=32)
+        inst.add_port('RFDC_M_AXI_rready',  'RFDC_M_AXI_rready')
+        inst.add_port('RFDC_M_AXI_rresp',   'RFDC_M_AXI_rresp', width=2)
+        inst.add_port('RFDC_M_AXI_rvalid',  'RFDC_M_AXI_rvalid')
+        inst.add_port('RFDC_M_AXI_wdata',   'RFDC_M_AXI_wdata', width=32)
+        inst.add_port('RFDC_M_AXI_wready',  'RFDC_M_AXI_wready')
+        inst.add_port('RFDC_M_AXI_wstrb',   'RFDC_M_AXI_wstrb', width=4)
+        inst.add_port('RFDC_M_AXI_wvalid',  'RFDC_M_AXI_wvalid')
+
         clkparams = clk_factors(100, self.platform.user_clk_rate)
 
         inst_infr = top.get_instance('zcu111_infrastructure', 'zcu111_infr_inst')