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Removing those weird assign statements
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These are not required any more as the signals are connected up
directly.
It probably should have been done this way in the first place.
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wnew committed Sep 2, 2022
1 parent 2801e01 commit cb98882
Showing 1 changed file with 0 additions and 5 deletions.
5 changes: 0 additions & 5 deletions jasper_library/yellow_blocks/bram.py
Original file line number Diff line number Diff line change
Expand Up @@ -39,11 +39,6 @@ def modify_top(self,top):
top.add_signal(self.fullname + '_data_in', width=self.data_width)
top.add_signal(self.fullname + '_data_out', width=self.data_width)
top.add_signal(self.fullname + '_we', width=1)
# Weird assignments. TODO: figure out what on earth the naming convention is with AXI generation.
top.assign_signal(self.fullname + '_addr', self.unique_name + '_' + self.unique_name + '_addr')
top.assign_signal(self.fullname + '_data_in', self.unique_name + '_' + self.unique_name + '_data_in')
top.assign_signal(self.fullname + '_data_out', self.unique_name + '_' + self.unique_name + '_data_out')
top.assign_signal(self.fullname + '_we', self.unique_name + '_' + self.unique_name + '_we')

else:
module = 'wb_bram'
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