dts: qemu_xtensa/xt-sim: Enable device tree support

patch enables dts support for boards qemu_xtensa and xt-sim

Signed-off-by: Savinay Dharmappa <[email protected]>

boards/xtensa/qemu_xtensa/Kconfig.board

@@ -6,4 +6,5 @@
 config  BOARD_QEMU_XTENSA
 	bool "Xtensa emulation using QEMU"
 	depends on SOC_XTENSA_SAMPLE_CONTROLLER
+	select HAS_DTS
 	select QEMU_TARGET

boards/xtensa/qemu_xtensa/qemu_xtensa.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "sample_controller.dtsi"
+
+/ {
+	model = "qemu_xtensa";
+	compatible = "xtensa, sample_controller";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};

boards/xtensa/xt-sim/Kconfig.board

@@ -6,3 +6,4 @@
 config BOARD_XT_SIM
 	bool "Xtensa Development ISS"
 	depends on SIMULATOR_XTENSA
+	select HAS_DTS

boards/xtensa/xt-sim/xt-sim.dts

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include "sample_controller.dtsi"
+
+/ {
+	model = "xt-sim";
+	compatible = "xtensa,sample_controller";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};

dts/xtensa/sample_controller.dtsi

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "sample_controller";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@60000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60000000 0x4000000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+	};
+};

soc/xtensa/sample_controller/linker.ld

@@ -16,6 +16,7 @@
 #include <autoconf.h>
 #include <linker/sections.h>
 
+#include <generated_dts_board.h>
 #include <linker/linker-defs.h>
 #include <linker/linker-tool.h>