fixed oversight

slaclab · Oct 15, 2024 · 8d3f2d6 · 8d3f2d6
1 parent 440eb48
commit 8d3f2d6
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/ethernet/RoCEv2/README.md b/ethernet/RoCEv2/README.md
@@ -1,5 +1,3 @@
-@FilMarini: Please write up some text about how these modules were auto-generated from BlueRdma
-
 # Hardware Implementation of RoCEv2 Engine
 This folder contains files generated from Bluespec SystemVerilog (BSV) source code located in different repositories: [blue-rdma](https://github.com/datenlord/blue-rdma), [blue-crc](https://github.com/datenlord/blue-crc)
 
@@ -16,4 +14,4 @@ The modifications consists in:
 ## License information
 The BSV-generated files follow the licensing terms from the original repositories. A copy of the original license can be found in the folders.
 
-Please ensure compliance with both licenses when using or modifying these files.
+Please ensure compliance with both licenses when using or modifying these files.