Modified CNF definition values

Audited all CNFx register definitions for baud-rates to confirm sample point location, SAM bit status, and SJW status. Changed all baud rates so that SAM bit is set (triple sample), SJW is half or less than PS2, and the sample point is at 75% or better where possible. This should help increase the reliability of the protocol controller. This was done for 8, 16, and 20MHz crystals frequencies.
sparrowme · Oct 10, 2017 · ece730c · ece730c
1 parent 7008cba
commit ece730c
Showing 1 changed file with 103 additions and 103 deletions.
diff --git a/mcp_can_dfs.h b/mcp_can_dfs.h
@@ -151,10 +151,10 @@
 #define MCP_RXB1SIDH    0x71
 
 
-#define MCP_TX_INT          0x1C                                    // Enable all transmit interrup ts
-#define MCP_TX01_INT        0x0C                                    // Enable TXB0 and TXB1 interru pts
-#define MCP_RX_INT          0x03                                    // Enable receive interrupts
-#define MCP_NO_INT          0x00                                    // Disable all interrupts
+#define MCP_TX_INT          0x1C                                    /* Enable all transmit interrup ts  */
+#define MCP_TX01_INT        0x0C                                    /* Enable TXB0 and TXB1 interru pts */
+#define MCP_RX_INT          0x03                                    /* Enable receive interrupts        */
+#define MCP_NO_INT          0x00                                    /* Disable all interrupts           */
 
 #define MCP_TX01_MASK       0x14
 #define MCP_TX_MASK        0x54
@@ -249,155 +249,155 @@
 /*
  *  Speed 8M
  */
-#define MCP_8MHz_1000kBPS_CFG1 (0x00)
-#define MCP_8MHz_1000kBPS_CFG2 (0x80)
-#define MCP_8MHz_1000kBPS_CFG3 (0x80)
+#define MCP_8MHz_1000kBPS_CFG1 (0x00)  
+#define MCP_8MHz_1000kBPS_CFG2 (0xC0)  /* Enabled SAM bit     */
+#define MCP_8MHz_1000kBPS_CFG3 (0x80)  /* Sample point at 75% */
 
 #define MCP_8MHz_500kBPS_CFG1 (0x00)
-#define MCP_8MHz_500kBPS_CFG2 (0x90)
-#define MCP_8MHz_500kBPS_CFG3 (0x82)
+#define MCP_8MHz_500kBPS_CFG2 (0xD1)   /* Enabled SAM bit     */
+#define MCP_8MHz_500kBPS_CFG3 (0x81)   /* Sample point at 75% */
 
-#define MCP_8MHz_250kBPS_CFG1 (0x00)
-#define MCP_8MHz_250kBPS_CFG2 (0xB1)
-#define MCP_8MHz_250kBPS_CFG3 (0x85)
+#define MCP_8MHz_250kBPS_CFG1 (0x80)   /* Increased SJW       */
+#define MCP_8MHz_250kBPS_CFG2 (0xE5)   /* Enabled SAM bit     */
+#define MCP_8MHz_250kBPS_CFG3 (0x83)   /* Sample point at 75% */
 
-#define MCP_8MHz_200kBPS_CFG1 (0x00)
-#define MCP_8MHz_200kBPS_CFG2 (0xB4)
-#define MCP_8MHz_200kBPS_CFG3 (0x86)
+#define MCP_8MHz_200kBPS_CFG1 (0x80)   /* Increased SJW       */
+#define MCP_8MHz_200kBPS_CFG2 (0xF6)   /* Enabled SAM bit     */
+#define MCP_8MHz_200kBPS_CFG3 (0x84)   /* Sample point at 75% */
 
-#define MCP_8MHz_125kBPS_CFG1 (0x01)
-#define MCP_8MHz_125kBPS_CFG2 (0xB1)
-#define MCP_8MHz_125kBPS_CFG3 (0x85)
+#define MCP_8MHz_125kBPS_CFG1 (0x81)   /* Increased SJW       */
+#define MCP_8MHz_125kBPS_CFG2 (0xE5)   /* Enabled SAM bit     */
+#define MCP_8MHz_125kBPS_CFG3 (0x83)   /* Sample point at 75% */
 
-#define MCP_8MHz_100kBPS_CFG1 (0x01)
-#define MCP_8MHz_100kBPS_CFG2 (0xB4)
-#define MCP_8MHz_100kBPS_CFG3 (0x86)
+#define MCP_8MHz_100kBPS_CFG1 (0x81)   /* Increased SJW       */
+#define MCP_8MHz_100kBPS_CFG2 (0xF6)   /* Enabled SAM bit     */
+#define MCP_8MHz_100kBPS_CFG3 (0x84)   /* Sample point at 75% */
 
-#define MCP_8MHz_80kBPS_CFG1 (0x01)
-#define MCP_8MHz_80kBPS_CFG2 (0xBF)
-#define MCP_8MHz_80kBPS_CFG3 (0x87)
+#define MCP_8MHz_80kBPS_CFG1 (0x84)    /* Increased SJW       */
+#define MCP_8MHz_80kBPS_CFG2 (0xD3)    /* Enabled SAM bit     */
+#define MCP_8MHz_80kBPS_CFG3 (0x81)    /* Sample point at 75% */
 
-#define MCP_8MHz_50kBPS_CFG1 (0x03)
-#define MCP_8MHz_50kBPS_CFG2 (0xB4)
-#define MCP_8MHz_50kBPS_CFG3 (0x86)
+#define MCP_8MHz_50kBPS_CFG1 (0x84)    /* Increased SJW       */
+#define MCP_8MHz_50kBPS_CFG2 (0xE5)    /* Enabled SAM bit     */
+#define MCP_8MHz_50kBPS_CFG3 (0x83)    /* Sample point at 75% */
 
-#define MCP_8MHz_40kBPS_CFG1 (0x03)
-#define MCP_8MHz_40kBPS_CFG2 (0xBF)
-#define MCP_8MHz_40kBPS_CFG3 (0x87)
+#define MCP_8MHz_40kBPS_CFG1 (0x84)    /* Increased SJW       */
+#define MCP_8MHz_40kBPS_CFG2 (0xF6)    /* Enabled SAM bit     */
+#define MCP_8MHz_40kBPS_CFG3 (0x84)    /* Sample point at 75% */
 
-#define MCP_8MHz_33k3BPS_CFG1 (0x47)
-#define MCP_8MHz_33k3BPS_CFG2 (0xE2)
-#define MCP_8MHz_33k3BPS_CFG3 (0x85)
+#define MCP_8MHz_33k3BPS_CFG1 (0x85)   /* Increased SJW       */
+#define MCP_8MHz_33k3BPS_CFG2 (0xF6)   /* Enabled SAM bit     */
+#define MCP_8MHz_33k3BPS_CFG3 (0x84)   /* Sample point at 75% */
 
-#define MCP_8MHz_31k25BPS_CFG1 (0x07)
-#define MCP_8MHz_31k25BPS_CFG2 (0xA4)
-#define MCP_8MHz_31k25BPS_CFG3 (0x84)
+#define MCP_8MHz_31k25BPS_CFG1 (0x87)  /* Increased SJW       */
+#define MCP_8MHz_31k25BPS_CFG2 (0xE5)  /* Enabled SAM bit     */
+#define MCP_8MHz_31k25BPS_CFG3 (0x83)  /* Sample point at 75% */
 
-#define MCP_8MHz_20kBPS_CFG1 (0x07)
-#define MCP_8MHz_20kBPS_CFG2 (0xBF)
-#define MCP_8MHz_20kBPS_CFG3 (0x87)
+#define MCP_8MHz_20kBPS_CFG1 (0x89)    /* Increased SJW       */
+#define MCP_8MHz_20kBPS_CFG2 (0xF6)    /* Enabled SAM bit     */
+#define MCP_8MHz_20kBPS_CFG3 (0x84)    /* Sample point at 75% */
 
-#define MCP_8MHz_10kBPS_CFG1 (0x0F)
-#define MCP_8MHz_10kBPS_CFG2 (0xBF)
-#define MCP_8MHz_10kBPS_CFG3 (0x87)
+#define MCP_8MHz_10kBPS_CFG1 (0x93)    /* Increased SJW       */
+#define MCP_8MHz_10kBPS_CFG2 (0xF6)    /* Enabled SAM bit     */
+#define MCP_8MHz_10kBPS_CFG3 (0x84)    /* Sample point at 75% */
 
-#define MCP_8MHz_5kBPS_CFG1 (0x1F)
-#define MCP_8MHz_5kBPS_CFG2 (0xBF)
-#define MCP_8MHz_5kBPS_CFG3 (0x87)
+#define MCP_8MHz_5kBPS_CFG1 (0xA7)     /* Increased SJW       */
+#define MCP_8MHz_5kBPS_CFG2 (0xF6)     /* Enabled SAM bit     */
+#define MCP_8MHz_5kBPS_CFG3 (0x84)     /* Sample point at 75% */
 
 /*
  *  speed 16M
  */
 #define MCP_16MHz_1000kBPS_CFG1 (0x00)
-#define MCP_16MHz_1000kBPS_CFG2 (0xD0)
-#define MCP_16MHz_1000kBPS_CFG3 (0x82)
+#define MCP_16MHz_1000kBPS_CFG2 (0xCA)
+#define MCP_16MHz_1000kBPS_CFG3 (0x81)    /* Sample point at 75% */
 
-#define MCP_16MHz_500kBPS_CFG1 (0x00)
-#define MCP_16MHz_500kBPS_CFG2 (0xF0)
-#define MCP_16MHz_500kBPS_CFG3 (0x86)
+#define MCP_16MHz_500kBPS_CFG1 (0x40)     /* Increased SJW       */
+#define MCP_16MHz_500kBPS_CFG2 (0xE5)
+#define MCP_16MHz_500kBPS_CFG3 (0x83)     /* Sample point at 75% */
 
 #define MCP_16MHz_250kBPS_CFG1 (0x41)
-#define MCP_16MHz_250kBPS_CFG2 (0xF1)
-#define MCP_16MHz_250kBPS_CFG3 (0x85)
+#define MCP_16MHz_250kBPS_CFG2 (0xE5)
+#define MCP_16MHz_250kBPS_CFG3 (0x83)     /* Sample point at 75% */
 
-#define MCP_16MHz_200kBPS_CFG1 (0x01)
-#define MCP_16MHz_200kBPS_CFG2 (0xFA)
-#define MCP_16MHz_200kBPS_CFG3 (0x87)
+#define MCP_16MHz_200kBPS_CFG1 (0x41)     /* Increased SJW       */
+#define MCP_16MHz_200kBPS_CFG2 (0xF6)
+#define MCP_16MHz_200kBPS_CFG3 (0x84)     /* Sample point at 75% */
 
-#define MCP_16MHz_125kBPS_CFG1 (0x03)
-#define MCP_16MHz_125kBPS_CFG2 (0xF0)
-#define MCP_16MHz_125kBPS_CFG3 (0x86)
+#define MCP_16MHz_125kBPS_CFG1 (0x43)     /* Increased SJW       */
+#define MCP_16MHz_125kBPS_CFG2 (0xE5)
+#define MCP_16MHz_125kBPS_CFG3 (0x83)     /* Sample point at 75% */
 
-#define MCP_16MHz_100kBPS_CFG1 (0x03)
-#define MCP_16MHz_100kBPS_CFG2 (0xFA)
-#define MCP_16MHz_100kBPS_CFG3 (0x87)
+#define MCP_16MHz_100kBPS_CFG1 (0x44)     /* Increased SJW       */
+#define MCP_16MHz_100kBPS_CFG2 (0xE5)
+#define MCP_16MHz_100kBPS_CFG3 (0x83)     /* Sample point at 75% */
 
-#define MCP_16MHz_80kBPS_CFG1 (0x03)
-#define MCP_16MHz_80kBPS_CFG2 (0xFF)
-#define MCP_16MHz_80kBPS_CFG3 (0x87)
+#define MCP_16MHz_80kBPS_CFG1 (0x44)      /* Increased SJW       */
+#define MCP_16MHz_80kBPS_CFG2 (0xF6)
+#define MCP_16MHz_80kBPS_CFG3 (0x84)      /* Sample point at 75% */
 
-#define MCP_16MHz_50kBPS_CFG1 (0x07)
-#define MCP_16MHz_50kBPS_CFG2 (0xFA)
-#define MCP_16MHz_50kBPS_CFG3 (0x87)
+#define MCP_16MHz_50kBPS_CFG1 (0x47)      /* Increased SJW       */
+#define MCP_16MHz_50kBPS_CFG2 (0xF6)
+#define MCP_16MHz_50kBPS_CFG3 (0x84)      /* Sample point at 75% */
 
-#define MCP_16MHz_40kBPS_CFG1 (0x07)
-#define MCP_16MHz_40kBPS_CFG2 (0xFF)
-#define MCP_16MHz_40kBPS_CFG3 (0x87)
+#define MCP_16MHz_40kBPS_CFG1 (0x49)      /* Increased SJW       */
+#define MCP_16MHz_40kBPS_CFG2 (0xF6)
+#define MCP_16MHz_40kBPS_CFG3 (0x84)      /* Sample point at 75% */
 
 #define MCP_16MHz_33k3BPS_CFG1 (0x4E)
-#define MCP_16MHz_33k3BPS_CFG2 (0xF1)
-#define MCP_16MHz_33k3BPS_CFG3 (0x85)
+#define MCP_16MHz_33k3BPS_CFG2 (0xE5)
+#define MCP_16MHz_33k3BPS_CFG3 (0x83)     /* Sample point at 75% */
 
-#define MCP_16MHz_20kBPS_CFG1 (0x0F)
-#define MCP_16MHz_20kBPS_CFG2 (0xFF)
-#define MCP_16MHz_20kBPS_CFG3 (0x87)
+#define MCP_16MHz_20kBPS_CFG1 (0x53)      /* Increased SJW       */
+#define MCP_16MHz_20kBPS_CFG2 (0xF6)
+#define MCP_16MHz_20kBPS_CFG3 (0x84)      /* Sample point at 75% */
 
-#define MCP_16MHz_10kBPS_CFG1 (0x1F)
-#define MCP_16MHz_10kBPS_CFG2 (0xFF)
-#define MCP_16MHz_10kBPS_CFG3 (0x87)
+#define MCP_16MHz_10kBPS_CFG1 (0x67)      /* Increased SJW       */
+#define MCP_16MHz_10kBPS_CFG2 (0xF6)
+#define MCP_16MHz_10kBPS_CFG3 (0x84)      /* Sample point at 75% */
 
 #define MCP_16MHz_5kBPS_CFG1 (0x3F)
 #define MCP_16MHz_5kBPS_CFG2 (0xFF)
-#define MCP_16MHz_5kBPS_CFG3 (0x87)
+#define MCP_16MHz_5kBPS_CFG3 (0x87)       /* Sample point at 68% */
 
 /*
  *  speed 20M
  */
 #define MCP_20MHz_1000kBPS_CFG1 (0x00)
 #define MCP_20MHz_1000kBPS_CFG2 (0xD9)
-#define MCP_20MHz_1000kBPS_CFG3 (0x82)
+#define MCP_20MHz_1000kBPS_CFG3 (0x82)     /* Sample point at 80% */
 
-#define MCP_20MHz_500kBPS_CFG1 (0x00)
-#define MCP_20MHz_500kBPS_CFG2 (0xFA)
-#define MCP_20MHz_500kBPS_CFG3 (0x87)
+#define MCP_20MHz_500kBPS_CFG1 (0x40)     /* Increased SJW       */
+#define MCP_20MHz_500kBPS_CFG2 (0xF6)
+#define MCP_20MHz_500kBPS_CFG3 (0x84)     /* Sample point at 75% */
 
-#define MCP_20MHz_250kBPS_CFG1 (0x41)
-#define MCP_20MHz_250kBPS_CFG2 (0xFB)
-#define MCP_20MHz_250kBPS_CFG3 (0x86)
+#define MCP_20MHz_250kBPS_CFG1 (0x41)     /* Increased SJW       */
+#define MCP_20MHz_250kBPS_CFG2 (0xF6)
+#define MCP_20MHz_250kBPS_CFG3 (0x84)     /* Sample point at 75% */
 
-#define MCP_20MHz_200kBPS_CFG1 (0x01)
-#define MCP_20MHz_200kBPS_CFG2 (0xFF)
-#define MCP_20MHz_200kBPS_CFG3 (0x87)
+#define MCP_20MHz_200kBPS_CFG1 (0x44)     /* Increased SJW       */
+#define MCP_20MHz_200kBPS_CFG2 (0xD3)
+#define MCP_20MHz_200kBPS_CFG3 (0x81)     /* Sample point at 80% */
 
-#define MCP_20MHz_125kBPS_CFG1 (0x03)
-#define MCP_20MHz_125kBPS_CFG2 (0xFA)
-#define MCP_20MHz_125kBPS_CFG3 (0x87)
+#define MCP_20MHz_125kBPS_CFG1 (0x44)     /* Increased SJW       */
+#define MCP_20MHz_125kBPS_CFG2 (0xE5)
+#define MCP_20MHz_125kBPS_CFG3 (0x83)     /* Sample point at 75% */
 
-#define MCP_20MHz_100kBPS_CFG1 (0x04)
-#define MCP_20MHz_100kBPS_CFG2 (0xFA)
-#define MCP_20MHz_100kBPS_CFG3 (0x87)
+#define MCP_20MHz_100kBPS_CFG1 (0x44)     /* Increased SJW       */
+#define MCP_20MHz_100kBPS_CFG2 (0xF6)
+#define MCP_20MHz_100kBPS_CFG3 (0x84)     /* Sample point at 75% */
 
-#define MCP_20MHz_80kBPS_CFG1 (0x04)
+#define MCP_20MHz_80kBPS_CFG1 (0xC4)      /* Increased SJW       */
 #define MCP_20MHz_80kBPS_CFG2 (0xFF)
-#define MCP_20MHz_80kBPS_CFG3 (0x87)
+#define MCP_20MHz_80kBPS_CFG3 (0x87)      /* Sample point at 68% */
 
-#define MCP_20MHz_50kBPS_CFG1 (0x09)
-#define MCP_20MHz_50kBPS_CFG2 (0xFA)
-#define MCP_20MHz_50kBPS_CFG3 (0x87)
+#define MCP_20MHz_50kBPS_CFG1 (0x49)      /* Increased SJW       */
+#define MCP_20MHz_50kBPS_CFG2 (0xF6)
+#define MCP_20MHz_50kBPS_CFG3 (0x84)      /* Sample point at 75% */
 
-#define MCP_20MHz_40kBPS_CFG1 (0x09)
-#define MCP_20MHz_40kBPS_CFG2 (0xFF)
-#define MCP_20MHz_40kBPS_CFG3 (0x87)
+#define MCP_20MHz_40kBPS_CFG1 (0x18)
+#define MCP_20MHz_40kBPS_CFG2 (0xD3)
+#define MCP_20MHz_40kBPS_CFG3 (0x81)      /* Sample point at 80% */
 
 
 #define MCPDEBUG        (0)