Chisel Learning Journey

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Generator Bootcamp Material: Learn Chisel the Right Way

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

4 stage, in-order, compute RISC-V core based on the CV32E40P

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

4 stage, in-order, secure RISC-V core based on the CV32E40P

CORE-V Family of RISC-V Cores

OmniXtend cache coherence protocol

Coroutine Co-simulation Test Bench

Working draft of the proposed RISC-V V vector extension

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

VeeR EH1 core

FuseSoC-based SoC for VeeR EH1 and EL2

Rocket Chip Generator

Verilator open-source SystemVerilog simulator and lint system

Test suite designed to check compliance with the SystemVerilog standard.

Chisel: A Modern Hardware Design Language

Random instruction generator for RISC-V processor verification

VeeR EL2 Core

FPGA reference design for the the Swerv EH1 Core

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

Density test bench for RISCV - "Compress extension"

Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...