Generic Register Interface (contains various adapters)

A utility for Composing FPGA designs from Peripherals

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

An easy-to-use, still-in-development RISC-V 32-bit instruction-accurate (IA) simulator.

Setup scripts and files needed to compile CoreMark on RISC-V

Neovim file explorer: edit your filesystem like a buffer

Neovim support for the Lean theorem prover

Mirror of https://git.tecosaur.net/tec/org-pandoc-import

Zstandard - Fast real-time compression algorithm

Experimental flows using nextpnr for Xilinx devices

RISC-V Processor Trace Specification

Fork of OpenOCD that has RISC-V support

Invoke is a leading creative engine for Stable Diffusion models, empowering professionals, artists, and enthusiasts to generate and create visual media using the latest AI-driven technologies. The …

Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

Bluespec Compiler (BSC)

Spins of Grant Searle's MultiComp project on various hardware

Altera JTAG UART wrapper for Bluespec

Mini CPU design with JTAG UART support

Official OpenOCD Read-Only Mirror (no pull requests)

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

A fast JSON parser/generator for C++ with both SAX/DOM style API

YosysHQ SVA AXI Properties

RISC-V Proxy Kernel

OpenTitan: Open source silicon root of trust

Simple single-port AXI memory interface

Sail RISC-V model

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX