target/ppc: Add SPR ASDR

The Access Segment Descriptor Register (ASDR) provides information about the storage element when taking a hypervisor storage interrupt. When performing nested radix address translation, this is normally the guest real address. This register is present on POWER9 processors and later. Implement the ADSR, note read and write access is limited to the hypervisor. Signed-off-by: Suraj Jitindar Singh <[email protected]> Reviewed-by: David Gibson <[email protected]> Signed-off-by: Cédric Le Goater <[email protected]> Message-Id: <[email protected]> Signed-off-by: David Gibson <[email protected]>
stefanha · Dec 16, 2019 · 32d0f0d · 32d0f0d
1 parent 5cc7e69
commit 32d0f0d
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diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
@@ -1778,6 +1778,7 @@ typedef PowerPCCPU ArchCPU;
 #define SPR_MPC_MD_DBRAM1     (0x32A)
 #define SPR_RCPU_L2U_RA3      (0x32B)
 #define SPR_TAR               (0x32F)
+#define SPR_ASDR              (0x330)
 #define SPR_IC                (0x350)
 #define SPR_VTB               (0x351)
 #define SPR_MMCRC             (0x353)

diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
@@ -8295,6 +8295,12 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
                         SPR_NOACCESS, SPR_NOACCESS,
                         &spr_read_generic, &spr_write_ptcr,
                         KVM_REG_PPC_PTCR, 0x00000000);
+    /* Address Segment Descriptor Register */
+    spr_register_hv(env, SPR_ASDR, "ASDR",
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    SPR_NOACCESS, SPR_NOACCESS,
+                    &spr_read_generic, &spr_write_generic,
+                    0x0000000000000000);
 #endif
 }