[rtl/system_integration] add README

rtl/system_integration/README.md

@@ -0,0 +1,21 @@
+## Processor System Integration
+
+### `neorv32_litex_core_complex.vhd`
+
+Pre-configured top entity wrapper for integration within the [LiteX](https://github.com/enjoy-digital/litex) SoC builder framework.
+
+> [!TIP]
+> See the user guide's [`core/mem`](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support) section for more information.
+
+### `neorv32_vivado_ip.vhd`
+
+Processor top entity with optional AXI4-Lite and AXI4-Stream interfaces. Dedicated for integration as custom IP block within AMD Vivado.
+Run the provided packaging script in the Vivado TCL shell to generate a NEORV32 IP block:
+
+```tcl
+source neorv32_vivado_ip.tcl
+```
+
+> [!TIP]
+> See the user guide's [UG: Packaging the Processor as Vivado IP Block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block)
+section for more information and step-by-step instructions for generating a NEORV32 IP module.