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platform/x86: ISST: Add Intel Speed Select mailbox interface via PCI
Add an IOCTL to send mailbox commands to PUNIT using PUNIT PCI device. A limited set of mailbox commands can be sent to PUNIT. This MMIO interface is used by the intel-speed-select tool under tools/x86/power to enumerate and control Intel Speed Select features. The MBOX commands ids and semantics of the message can be checked from the source code of the tool. Signed-off-by: Srinivas Pandruvada <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
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199 changes: 199 additions & 0 deletions
199
drivers/platform/x86/intel_speed_select_if/isst_if_mbox_pci.c
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// SPDX-License-Identifier: GPL-2.0 | ||
/* | ||
* Intel Speed Select Interface: Mbox via PCI Interface | ||
* Copyright (c) 2019, Intel Corporation. | ||
* All rights reserved. | ||
* | ||
* Author: Srinivas Pandruvada <[email protected]> | ||
*/ | ||
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#include <linux/cpufeature.h> | ||
#include <linux/module.h> | ||
#include <linux/pci.h> | ||
#include <linux/sched/signal.h> | ||
#include <linux/uaccess.h> | ||
#include <uapi/linux/isst_if.h> | ||
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#include "isst_if_common.h" | ||
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#define PUNIT_MAILBOX_DATA 0xA0 | ||
#define PUNIT_MAILBOX_INTERFACE 0xA4 | ||
#define PUNIT_MAILBOX_BUSY_BIT 31 | ||
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/* | ||
* Commands has variable amount of processing time. Most of the commands will | ||
* be done in 0-3 tries, but some takes up to 50. | ||
* The real processing time was observed as 25us for the most of the commands | ||
* at 2GHz. It is possible to optimize this count taking samples on customer | ||
* systems. | ||
*/ | ||
#define OS_MAILBOX_RETRY_COUNT 50 | ||
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struct isst_if_device { | ||
struct mutex mutex; | ||
}; | ||
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static int isst_if_mbox_cmd(struct pci_dev *pdev, | ||
struct isst_if_mbox_cmd *mbox_cmd) | ||
{ | ||
u32 retries, data; | ||
int ret; | ||
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/* Poll for rb bit == 0 */ | ||
retries = OS_MAILBOX_RETRY_COUNT; | ||
do { | ||
ret = pci_read_config_dword(pdev, PUNIT_MAILBOX_INTERFACE, | ||
&data); | ||
if (ret) | ||
return ret; | ||
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if (data & BIT_ULL(PUNIT_MAILBOX_BUSY_BIT)) { | ||
ret = -EBUSY; | ||
continue; | ||
} | ||
ret = 0; | ||
break; | ||
} while (--retries); | ||
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if (ret) | ||
return ret; | ||
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/* Write DATA register */ | ||
ret = pci_write_config_dword(pdev, PUNIT_MAILBOX_DATA, | ||
mbox_cmd->req_data); | ||
if (ret) | ||
return ret; | ||
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/* Write command register */ | ||
data = BIT_ULL(PUNIT_MAILBOX_BUSY_BIT) | | ||
(mbox_cmd->parameter & GENMASK_ULL(13, 0)) << 16 | | ||
(mbox_cmd->sub_command << 8) | | ||
mbox_cmd->command; | ||
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ret = pci_write_config_dword(pdev, PUNIT_MAILBOX_INTERFACE, data); | ||
if (ret) | ||
return ret; | ||
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/* Poll for rb bit == 0 */ | ||
retries = OS_MAILBOX_RETRY_COUNT; | ||
do { | ||
ret = pci_read_config_dword(pdev, PUNIT_MAILBOX_INTERFACE, | ||
&data); | ||
if (ret) | ||
return ret; | ||
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if (data & BIT_ULL(PUNIT_MAILBOX_BUSY_BIT)) { | ||
ret = -EBUSY; | ||
continue; | ||
} | ||
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if (data & 0xff) | ||
return -ENXIO; | ||
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ret = pci_read_config_dword(pdev, PUNIT_MAILBOX_DATA, &data); | ||
if (ret) | ||
return ret; | ||
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mbox_cmd->resp_data = data; | ||
ret = 0; | ||
break; | ||
} while (--retries); | ||
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return ret; | ||
} | ||
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static long isst_if_mbox_proc_cmd(u8 *cmd_ptr, int *write_only, int resume) | ||
{ | ||
struct isst_if_mbox_cmd *mbox_cmd; | ||
struct isst_if_device *punit_dev; | ||
struct pci_dev *pdev; | ||
int ret; | ||
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mbox_cmd = (struct isst_if_mbox_cmd *)cmd_ptr; | ||
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if (isst_if_mbox_cmd_invalid(mbox_cmd)) | ||
return -EINVAL; | ||
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if (isst_if_mbox_cmd_set_req(mbox_cmd) && !capable(CAP_SYS_ADMIN)) | ||
return -EPERM; | ||
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pdev = isst_if_get_pci_dev(mbox_cmd->logical_cpu, 1, 30, 1); | ||
if (!pdev) | ||
return -EINVAL; | ||
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punit_dev = pci_get_drvdata(pdev); | ||
if (!punit_dev) | ||
return -EINVAL; | ||
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/* | ||
* Basically we are allowing one complete mailbox transaction on | ||
* a mapped PCI device at a time. | ||
*/ | ||
mutex_lock(&punit_dev->mutex); | ||
ret = isst_if_mbox_cmd(pdev, mbox_cmd); | ||
mutex_unlock(&punit_dev->mutex); | ||
if (ret) | ||
return ret; | ||
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*write_only = 0; | ||
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return 0; | ||
} | ||
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static const struct pci_device_id isst_if_mbox_ids[] = { | ||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, INTEL_CFG_MBOX_DEVID_0)}, | ||
{ 0 }, | ||
}; | ||
MODULE_DEVICE_TABLE(pci, isst_if_mbox_ids); | ||
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static int isst_if_mbox_probe(struct pci_dev *pdev, | ||
const struct pci_device_id *ent) | ||
{ | ||
struct isst_if_device *punit_dev; | ||
struct isst_if_cmd_cb cb; | ||
int ret; | ||
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punit_dev = devm_kzalloc(&pdev->dev, sizeof(*punit_dev), GFP_KERNEL); | ||
if (!punit_dev) | ||
return -ENOMEM; | ||
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ret = pcim_enable_device(pdev); | ||
if (ret) | ||
return ret; | ||
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mutex_init(&punit_dev->mutex); | ||
pci_set_drvdata(pdev, punit_dev); | ||
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memset(&cb, 0, sizeof(cb)); | ||
cb.cmd_size = sizeof(struct isst_if_mbox_cmd); | ||
cb.offset = offsetof(struct isst_if_mbox_cmds, mbox_cmd); | ||
cb.cmd_callback = isst_if_mbox_proc_cmd; | ||
cb.owner = THIS_MODULE; | ||
ret = isst_if_cdev_register(ISST_IF_DEV_MBOX, &cb); | ||
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if (ret) | ||
mutex_destroy(&punit_dev->mutex); | ||
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return ret; | ||
} | ||
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static void isst_if_mbox_remove(struct pci_dev *pdev) | ||
{ | ||
struct isst_if_device *punit_dev; | ||
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punit_dev = pci_get_drvdata(pdev); | ||
isst_if_cdev_unregister(ISST_IF_DEV_MBOX); | ||
mutex_destroy(&punit_dev->mutex); | ||
} | ||
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static struct pci_driver isst_if_pci_driver = { | ||
.name = "isst_if_mbox_pci", | ||
.id_table = isst_if_mbox_ids, | ||
.probe = isst_if_mbox_probe, | ||
.remove = isst_if_mbox_remove, | ||
}; | ||
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module_pci_driver(isst_if_pci_driver); | ||
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MODULE_LICENSE("GPL v2"); | ||
MODULE_DESCRIPTION("Intel speed select interface pci mailbox driver"); |
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