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Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index el…
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…imination more exactly for Thumb-2 to get better code gen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
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David Goodwin committed Jul 24, 2009
1 parent 74e5210 commit 5ff58b5
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Showing 16 changed files with 370 additions and 211 deletions.
38 changes: 30 additions & 8 deletions lib/Target/ARM/ARMBaseInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -513,7 +513,7 @@ unsigned
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
unsigned oc = MI->getOpcode();
if (oc == getOpcode(ARMII::LDR)) {
if (oc == getOpcode(ARMII::LDRrr)) {
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
Expand All @@ -523,6 +523,14 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
return MI->getOperand(0).getReg();
}
}
else if (oc == getOpcode(ARMII::LDRri)) {
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
else if ((oc == getOpcode(ARMII::FLDD)) ||
(oc == getOpcode(ARMII::FLDS))) {
if (MI->getOperand(1).isFI() &&
Expand All @@ -540,7 +548,7 @@ unsigned
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
unsigned oc = MI->getOpcode();
if (oc == getOpcode(ARMII::STR)) {
if (oc == getOpcode(ARMII::STRrr)) {
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
Expand All @@ -550,6 +558,14 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
return MI->getOperand(0).getReg();
}
}
else if (oc == getOpcode(ARMII::STRri)) {
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
else if ((oc == getOpcode(ARMII::FSTD)) ||
(oc == getOpcode(ARMII::FSTS))) {
if (MI->getOperand(1).isFI() &&
Expand Down Expand Up @@ -602,7 +618,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (I != MBB.end()) DL = I->getDebugLoc();

if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STR)))
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::STRrr)))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::DPRRegisterClass) {
Expand All @@ -626,7 +642,10 @@ ARMBaseInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == ARM::GPRRegisterClass) {
Opc = getOpcode(ARMII::STR);
if ((Addr.size() > 1) && Addr[1].isImm())
Opc = getOpcode(ARMII::STRri);
else
Opc = getOpcode(ARMII::STRrr);
} else if (RC == ARM::DPRRegisterClass) {
Opc = getOpcode(ARMII::FSTD);
} else {
Expand All @@ -651,7 +670,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (I != MBB.end()) DL = I->getDebugLoc();

if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDR)), DestReg)
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::LDRrr)), DestReg)
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::DPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FLDD)), DestReg)
Expand All @@ -671,7 +690,10 @@ loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == ARM::GPRRegisterClass) {
Opc = getOpcode(ARMII::LDR);
if ((Addr.size() > 1) && Addr[1].isImm())
Opc = getOpcode(ARMII::LDRri);
else
Opc = getOpcode(ARMII::LDRrr);
} else if (RC == ARM::DPRRegisterClass) {
Opc = getOpcode(ARMII::FLDD);
} else {
Expand Down Expand Up @@ -704,14 +726,14 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STR)))
NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::STRrr)))
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDR)))
NewMI = BuildMI(MF, MI->getDebugLoc(), get(getOpcode(ARMII::LDRrr)))
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |
Expand Down
13 changes: 4 additions & 9 deletions lib/Target/ARM/ARMBaseInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -177,9 +177,11 @@ namespace ARMII {
FLDS,
FSTD,
FSTS,
LDR,
LDRrr,
LDRri,
MOVr,
STR,
STRrr,
STRri,
SUBri,
SUBrs,
SUBrr,
Expand Down Expand Up @@ -215,13 +217,6 @@ class ARMBaseInstrInfo : public TargetInstrInfoImpl {
// Return the opcode that implements 'Op', or 0 if no opcode
virtual unsigned getOpcode(ARMII::Op Op) const =0;

// If 'opcode' is an instruction with an unsigned offset that also
// has a version with a signed offset, return the opcode for the
// version with the signed offset. In 'NumBits' return the number of
// bits for the signed offset.
virtual unsigned unsignedOffsetOpcodeToSigned(unsigned opcode,
unsigned *NumBits) const = 0;

// Return true if the block does not fall through.
virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;

Expand Down
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