Skip to content

Commit

Permalink
MachineInstr: addRegisterDefReadUndef() => setRegisterDefReadUndef()
Browse files Browse the repository at this point in the history
This way we can not only add but also remove read undef flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252678 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information
MatzeB committed Nov 11, 2015
1 parent dc3ae09 commit f98fd35
Show file tree
Hide file tree
Showing 3 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion include/llvm/CodeGen/MachineInstr.h
Original file line number Diff line number Diff line change
Expand Up @@ -1063,7 +1063,7 @@ class MachineInstr : public ilist_node<MachineInstr> {
/// Mark all subregister defs of register @p Reg with the undef flag.
/// This function is used when we determined to have a subregister def in an
/// otherwise undefined super register.
void addRegisterDefReadUndef(unsigned Reg);
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);

/// We have determined MI defines a register. Make sure there is an operand
/// defining Reg.
Expand Down
2 changes: 1 addition & 1 deletion lib/CodeGen/LiveIntervalAnalysis.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -490,7 +490,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
if (MRI->shouldTrackSubRegLiveness(VReg)) {
if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
MachineInstr *MI = getInstructionFromIndex(Def);
MI->addRegisterDefReadUndef(VReg);
MI->setRegisterDefReadUndef(VReg);
DeadBeforeDef = true;
}
}
Expand Down
4 changes: 2 additions & 2 deletions lib/CodeGen/MachineInstr.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1933,11 +1933,11 @@ void MachineInstr::clearRegisterDeads(unsigned Reg) {
}
}

void MachineInstr::addRegisterDefReadUndef(unsigned Reg) {
void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
continue;
MO.setIsUndef();
MO.setIsUndef(IsUndef);
}
}

Expand Down

0 comments on commit f98fd35

Please sign in to comment.