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Commits on Sep 6, 2016

• Formatting with clang-format patch r280700

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  Leny Kholodov

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  01dd3d9

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• [SelectionDAG] Simplify extract_subvector( insert_subvector ( Vec, In, Idx ), Idx ) -> In

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  RKSimon

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• [JumpThreading] Only write back branch-weight MDs for blocks that originally had PGO info

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  anemet

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• [Sparc][Leon] Corrected supported atomics size for processors supporting Leon CASA instruction back to 32 bits.

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  Chris Dewhurst

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• [mips] Tighten FastISel restrictions

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  Simon Dardis

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• [PPC] Claim stack frame before storing into it, if no red zone is present

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  Krzysztof Parzyszek

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• DebugInfo: use strongly typed enum for debug info flags

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  Leny Kholodov

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• [RegisterScavenger] Remove aliasing registers of operands from the candidate set

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  sbaranga-arm

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• [AVX-512] Fix masked VPERMI2PS isel when the index comes from a bitcast.

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  topperc

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• [X86] Remove unused encoding from IntrinsicType enum.

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  topperc

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• [X86] Fix indentation. NFC

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  topperc

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• ARM: workaround bundled operation predication

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  compnerd

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• Revert "DebugInfo: use strongly typed enum for debug info flags"

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  joker-eph

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• [LTO] Constify (NFC)

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  joker-eph

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• DebugInfo: use strongly typed enum for debug info flags

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  joker-eph

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• [AVX-512] Fix v8i64 shift by immediate lowering on 32-bit targets.

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  topperc

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• CodeGen: ensure that libcalls are always AAPCS CC

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  compnerd

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Commits on Sep 5, 2016

• [AVX-512] Teach fastisel load/store handling to use EVEX encoded instructions for 128/256-bit vectors and scalar single/double.

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  topperc

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• [Coroutines] Part12: Handle alloca address-taken

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  GorNishanov

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• [InstCombine] don't assert that division-by-constant has been folded (PR30281)

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  rotateright

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• [InstCombine] revert r280637 because it causes test failures on an ARM bot

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  rotateright

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• [AVX-512] Integrate mask register copying more completely into X86InstrInfo::copyPhysReg and simplify. No functional change intended.

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  topperc

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• [WebAssembly] Unbreak the build.

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  d0k

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• [AMDGPU] Refactor FLAT TD instructions

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  vpykhtin

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• [Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc}

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  James Molloy

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• [AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Explicitly zero upper bits.

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  Igor Breger

  committed
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• [X86] Make some static arrays of opcodes const and shrink to uint16_t. NFC

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  topperc

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• [AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit vectors with AVX512, but not VLX. We should use the VEX opcodes and trust the register allocator to not use the extended XMM/YMM registe…

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  topperc

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• [Coroutines] Part11: Add final suspend handling.

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  GorNishanov

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• [X86] Remove FsVMOVAPSrm/FsVMOVAPDrm/FsMOVAPSrm/FsMOVAPDrm. Due to their placement in the td file they had lower precedence than (V)MOVSS/SD and could almost never be selected.

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  topperc

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Commits on Sep 4, 2016

• [InstCombine] allow icmp (and X, C2), C1 folds for splat constant vectors

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  rotateright

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• [AVX-512] Add EVEX encoded scalar FMA intrinsic instructions to isNonFoldablePartialRegisterLoad.

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  topperc

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• [AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div intrinsics and upgrade to native IR.

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  topperc

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• [ORC] Clone module flags metadata into the globals module in the

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  lhames

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• [InstCombine] recode icmp fold in a vector-friendly way; NFC

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  rotateright

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