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Commits on Mar 31, 2017

• AMDGPU/R600: Fix amdgpu alias analysis pass.

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Commits on Mar 6, 2017

• AMDGPU/R600: Fix ALU clause markers use detection

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Commits on Feb 25, 2017

• AMDGPU/SI: export s_waitcnt builtin

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Commits on Feb 23, 2017

• AMDGPU/SI: Fix trunc i16 pattern

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Commits on Feb 18, 2017

• AMDGPU/R600: Assert on infinite loop in EmitClauseMarkers

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Commits on Jan 20, 2017

• AMDGPU/R600: Serialize vector trunc stores to private AS

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Commits on Jan 16, 2017

• ADMGPU/EG,CM: Implement _noret global atomics

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Commits on Jan 11, 2017

• AMDGPU/EG,CM: Add fp16 conversion instructions

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Commits on Jan 6, 2017

• AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodes

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Commits on Jan 4, 2017

• AMDGPU/SI: Implement sendmsghalt intrinsic

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Commits on Dec 23, 2016

• AMDGPU: split ret/noret patterns for global atomics

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Commits on Nov 15, 2016

• AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument

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Commits on Sep 2, 2016

• AMDGPU/R600: EXTRACT_VECT_ELT should only bypass BUILD_VECTOR if the vectors have the same number of elements.

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• AMDGPU/R600: Expand unaligned writes to local and global AS

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• AMDGPU: Reorganize store tests

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Commits on Aug 29, 2016

• AMDGPU/R600: Cleanup DAGCombine

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• AMDGPU/R600: Remove MergeVectorStores from legalization

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Commits on Aug 27, 2016

• AMDGPU/R600: Enable Load combine

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Commits on Aug 15, 2016

• AMDGPU/R600: Convert buffer id to VTX_READ input

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Commits on Jul 25, 2016

• AMDGPU: Remove read_workdim intrinsic

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Commits on Jul 10, 2016

• AMDGPU/R600: Add implicitarg.ptr intrinsic

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Commits on Jul 4, 2016

• AMDGPU/R600: Add indentation to VTX and TEX fetch asm strings

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Commits on Jun 25, 2016

• AMDGPU/R600: Fix GlobalValue regressions.

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Commits on Jun 21, 2016

• AMDGPU: Remove gcc builtin names from workitem intrinsics

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• AMDGPU: Add implicitarg.ptr intrinsic.

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Commits on Jun 9, 2016

• SelectionDAG: Implement expansion of {S,U}MIN/MAX in integer legalization

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Commits on May 18, 2016

• AMDGPU: Fix incorrect simm check

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Commits on May 16, 2016

• AMDGPU/R600: Use correct number of vector elements when lowering private loads

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Commits on May 13, 2016

• AMDGPU: Unify LowerGlobalAddress

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• AMDGPU/R600: Fold global address operand

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• AMDGPU/R600: Implement memory loads from constant AS

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• AMDGPU/R600: Add support for emitting MCExpr

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• AMDGPU: Add support for MCExpr to instruction printer

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• AMDGPU/R600: Use machine operands instead of ints to track literals

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• AMDGPU/R600: There are other uses for ALU_LITERAL besides Imm

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