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ARM: pxa: separate the clock support into clock-{pxa2xx,pxa3xx}.c
Signed-off-by: Eric Miao <[email protected]>
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/* | ||
* linux/arch/arm/mach-pxa/clock-pxa2xx.c | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
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#include <linux/module.h> | ||
#include <linux/kernel.h> | ||
#include <linux/init.h> | ||
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#include <mach/pxa2xx-regs.h> | ||
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#include "clock.h" | ||
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void clk_pxa2xx_cken_enable(struct clk *clk) | ||
{ | ||
CKEN |= 1 << clk->cken; | ||
} | ||
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void clk_pxa2xx_cken_disable(struct clk *clk) | ||
{ | ||
CKEN &= ~(1 << clk->cken); | ||
} | ||
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const struct clkops clk_pxa2xx_cken_ops = { | ||
.enable = clk_pxa2xx_cken_enable, | ||
.disable = clk_pxa2xx_cken_disable, | ||
}; |
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/* | ||
* linux/arch/arm/mach-pxa/clock-pxa3xx.c | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License version 2 as | ||
* published by the Free Software Foundation. | ||
*/ | ||
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#include <linux/module.h> | ||
#include <linux/kernel.h> | ||
#include <linux/init.h> | ||
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#include <mach/pxa3xx-regs.h> | ||
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#include "clock.h" | ||
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/* Crystal clock: 13MHz */ | ||
#define BASE_CLK 13000000 | ||
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/* Ring Oscillator Clock: 60MHz */ | ||
#define RO_CLK 60000000 | ||
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#define ACCR_D0CS (1 << 26) | ||
#define ACCR_PCCE (1 << 11) | ||
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/* crystal frequency to static memory controller multiplier (SMCFS) */ | ||
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | ||
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */ | ||
static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; | ||
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/* | ||
* Get the clock frequency as reflected by CCSR and the turbo flag. | ||
* We assume these values have been applied via a fcs. | ||
* If info is not 0 we also display the current settings. | ||
*/ | ||
unsigned int pxa3xx_get_clk_frequency_khz(int info) | ||
{ | ||
unsigned long acsr, xclkcfg; | ||
unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; | ||
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/* Read XCLKCFG register turbo bit */ | ||
__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); | ||
t = xclkcfg & 0x1; | ||
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acsr = ACSR; | ||
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xl = acsr & 0x1f; | ||
xn = (acsr >> 8) & 0x7; | ||
hss = (acsr >> 14) & 0x3; | ||
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XL = xl * BASE_CLK; | ||
XN = xn * XL; | ||
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ro = acsr & ACCR_D0CS; | ||
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL); | ||
HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
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if (info) { | ||
pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", | ||
RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, | ||
(ro) ? "" : "in"); | ||
pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", | ||
XL / 1000000, (XL % 1000000) / 10000, xl); | ||
pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", | ||
XN / 1000000, (XN % 1000000) / 10000, xn, | ||
(t) ? "" : "in"); | ||
pr_info("HSIO bus clock: %d.%02dMHz\n", | ||
HSS / 1000000, (HSS % 1000000) / 10000); | ||
} | ||
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return CLK / 1000; | ||
} | ||
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/* | ||
* Return the current AC97 clock frequency. | ||
*/ | ||
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | ||
{ | ||
unsigned long rate = 312000000; | ||
unsigned long ac97_div; | ||
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ac97_div = AC97_DIV; | ||
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/* This may loose precision for some rates but won't for the | ||
* standard 24.576MHz. | ||
*/ | ||
rate /= (ac97_div >> 12) & 0x7fff; | ||
rate *= (ac97_div & 0xfff); | ||
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return rate; | ||
} | ||
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/* | ||
* Return the current HSIO bus clock frequency | ||
*/ | ||
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | ||
{ | ||
unsigned long acsr; | ||
unsigned int hss, hsio_clk; | ||
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acsr = ACSR; | ||
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hss = (acsr >> 14) & 0x3; | ||
hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
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return hsio_clk; | ||
} | ||
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void clk_pxa3xx_cken_enable(struct clk *clk) | ||
{ | ||
unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
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if (clk->cken < 32) | ||
CKENA |= mask; | ||
else | ||
CKENB |= mask; | ||
} | ||
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void clk_pxa3xx_cken_disable(struct clk *clk) | ||
{ | ||
unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
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if (clk->cken < 32) | ||
CKENA &= ~mask; | ||
else | ||
CKENB &= ~mask; | ||
} | ||
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const struct clkops clk_pxa3xx_cken_ops = { | ||
.enable = clk_pxa3xx_cken_enable, | ||
.disable = clk_pxa3xx_cken_disable, | ||
}; | ||
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const struct clkops clk_pxa3xx_hsio_ops = { | ||
.enable = clk_pxa3xx_cken_enable, | ||
.disable = clk_pxa3xx_cken_disable, | ||
.getrate = clk_pxa3xx_hsio_getrate, | ||
}; | ||
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const struct clkops clk_pxa3xx_ac97_ops = { | ||
.enable = clk_pxa3xx_cken_enable, | ||
.disable = clk_pxa3xx_cken_disable, | ||
.getrate = clk_pxa3xx_ac97_getrate, | ||
}; | ||
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static void clk_pout_enable(struct clk *clk) | ||
{ | ||
OSCC |= OSCC_PEN; | ||
} | ||
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static void clk_pout_disable(struct clk *clk) | ||
{ | ||
OSCC &= ~OSCC_PEN; | ||
} | ||
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const struct clkops clk_pxa3xx_pout_ops = { | ||
.enable = clk_pout_enable, | ||
.disable = clk_pout_disable, | ||
}; |
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