[AMDGPU] Implement wave64 DWARF register mapping

Summary:
Implement the DWARF register mapping described in
llvm/docs/AMDGPUUsage.rst

This is currently limited to wave64 VGPRs/AGPRs.

This also includes some minor changes in AMDGPUInstPrinter,
AMDGPUMCTargetDesc, and AMDGPUAsmParser to make generating CFI assembly
text and ELF sections possible to ease testing, although complete CFI
support is not yet implemented.

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74915

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

@@ -1989,6 +1989,7 @@ static unsigned getSpecialRegForName(StringRef RegName) {
     .Case("tma_hi", AMDGPU::TMA_HI)
     .Case("tba_lo", AMDGPU::TBA_LO)
     .Case("tba_hi", AMDGPU::TBA_HI)
+    .Case("pc", AMDGPU::PC_REG)
     .Case("null", AMDGPU::SGPR_NULL)
     .Default(AMDGPU::NoRegister);
 }

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

@@ -26,6 +26,10 @@
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
+void AMDGPUInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
+  OS << getRegisterName(RegNo);
+}
+
 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                   StringRef Annot, const MCSubtargetInfo &STI,
                                   raw_ostream &OS) {

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

@@ -23,6 +23,7 @@ class AMDGPUInstPrinter : public MCInstPrinter {
     : MCInstPrinter(MAI, MII, MRI) {}
 
   //Autogenerated by tblgen
+  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
   void printInstruction(const MCInst *MI, uint64_t Address,
                         const MCSubtargetInfo &STI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

@@ -61,7 +61,7 @@ static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
   if (TT.getArch() == Triple::r600)
     InitR600MCRegisterInfo(X, 0);
   else
-    InitAMDGPUMCRegisterInfo(X, 0);
+    InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG);
   return X;
 }
 

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

@@ -84,8 +84,7 @@ class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
 //  Declarations that describe the SI registers
 //===----------------------------------------------------------------------===//
 class SIReg <string n, bits<16> regIdx = 0> :
-  Register<n>,
-  DwarfRegNum<[!cast<int>(HWEncoding)]> {
+  Register<n> {
   let Namespace = "AMDGPU";
 
   // This is the not yet the complete register encoding. An additional
@@ -104,19 +103,25 @@ def FP_REG : SIReg<"fp", 0>;
 def SP_REG : SIReg<"sp", 0>;
 def SCRATCH_WAVE_OFFSET_REG : SIReg<"scratch_wave_offset", 0>;
 
+// Pseudo-register to represent the program-counter DWARF register.
+def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16]> {
+  // There is no physical register corresponding to a "program counter", but
+  // we need to encode the concept in debug information in order to represent
+  // things like the return value in unwind information.
+  let isArtificial = 1;
+}
+
 // VCC for 64-bit instructions
-def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
-          DwarfRegAlias<VCC_LO> {
+def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 106;
 }
 
-def EXEC_LO : SIReg<"exec_lo", 126>;
+def EXEC_LO : SIReg<"exec_lo", 126>, DwarfRegNum<[1]>;
 def EXEC_HI : SIReg<"exec_hi", 127>;
 
-def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>,
-           DwarfRegAlias<EXEC_LO> {
+def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 126;
@@ -151,8 +156,8 @@ def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
 def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>;
 def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>;
 
-def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>,
-                 DwarfRegAlias<XNACK_MASK_LO> {
+def XNACK_MASK :
+    RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 104;
@@ -162,8 +167,7 @@ def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI
 def TBA_LO : SIReg<"tba_lo", 108>;
 def TBA_HI : SIReg<"tba_hi", 109>;
 
-def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>,
-          DwarfRegAlias<TBA_LO> {
+def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 108;
@@ -172,8 +176,7 @@ def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>,
 def TMA_LO : SIReg<"tma_lo", 110>;
 def TMA_HI : SIReg<"tma_hi", 111>;
 
-def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>,
-          DwarfRegAlias<TMA_LO> {
+def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 110;
@@ -192,8 +195,7 @@ multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
 }
 
 class FlatReg <Register lo, Register hi, bits<16> encoding> :
-    RegisterWithSubRegs<"flat_scratch", [lo, hi]>,
-    DwarfRegAlias<lo> {
+    RegisterWithSubRegs<"flat_scratch", [lo, hi]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = encoding;
@@ -208,19 +210,25 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
 
 // SGPR registers
 foreach Index = 0-105 in {
-  def SGPR#Index : SIReg <"s"#Index, Index>;
+  def SGPR#Index :
+    SIReg <"s"#Index, Index>,
+    DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
 }
 
 // VGPR registers
 foreach Index = 0-255 in {
-  def VGPR#Index : SIReg <"v"#Index, Index> {
+  def VGPR#Index :
+      SIReg <"v"#Index, Index>,
+      DwarfRegNum<[!add(Index, 2560)]> {
     let HWEncoding{8} = 1;
   }
 }
 
 // AccVGPR registers
 foreach Index = 0-255 in {
-  def AGPR#Index : SIReg <"a"#Index, Index> {
+  def AGPR#Index :
+      SIReg <"a"#Index, Index>,
+      DwarfRegNum<[!add(Index, 3072)]> {
     let HWEncoding{8} = 1;
   }
 }

llvm/test/DebugInfo/AMDGPU/print-reg-name.s

@@ -0,0 +1,10 @@
+; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm %s | FileCheck %s
+
+; Check that we can print symbolic register operands in CFI instructions.
+
+.text
+f:
+.cfi_startproc
+; CHECK: .cfi_undefined s0
+.cfi_undefined s0
+.cfi_endproc

llvm/test/DebugInfo/AMDGPU/register-mapping.s

@@ -0,0 +1,37 @@
+; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj %s | llvm-dwarfdump -debug-frame - | FileCheck %s
+
+; Check that we implement the DWARF register mapping.
+
+.text
+f:
+.cfi_startproc
+; CHECK: CIE
+; CHECK: Return address column: 16
+
+; CHECK: FDE
+; CHECK: DW_CFA_undefined: reg16
+.cfi_undefined pc
+; CHECK: DW_CFA_undefined: reg17
+.cfi_undefined exec
+
+; CHECK: DW_CFA_undefined: reg32
+.cfi_undefined s0
+; CHECK: DW_CFA_undefined: reg95
+.cfi_undefined s63
+
+; CHECK: DW_CFA_undefined: reg1088
+.cfi_undefined s64
+; CHECK: DW_CFA_undefined: reg1129
+.cfi_undefined s105
+
+; CHECK: DW_CFA_undefined: reg2560
+.cfi_undefined v0
+; CHECK: DW_CFA_undefined: reg2815
+.cfi_undefined v255
+
+; CHECK: DW_CFA_undefined: reg3072
+.cfi_undefined a0
+; CHECK: DW_CFA_undefined: reg3327
+.cfi_undefined a255
+
+.cfi_endproc

llvm/test/DebugInfo/AMDGPU/variable-locations.ll

@@ -32,7 +32,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
 @GlobB = common addrspace(1) global i32 0, align 4, !dbg !6
 
 ; CHECK: {{.*}}DW_TAG_subprogram
-; CHECK: DW_AT_frame_base [DW_FORM_block1]	(DW_OP_reg9 SGPR9)
+; CHECK: DW_AT_frame_base [DW_FORM_block1]	(DW_OP_reg{{.*}} SGPR9)
 
 define amdgpu_kernel void @kernel1(
 ; CHECK: {{.*}}DW_TAG_formal_parameter