[snippy] Small refactoring

llvm/test/tools/llvm-snippy/codegen/rvv-no-available-instrs-pvill.yaml

@@ -36,4 +36,4 @@ histogram:
     - [VXOR_VX, 1.0]
     - [VZEXT_VF4, 1.0]
 
-# CHECK: We can not create any primary instruction in this context.
+# CHECK: error: We can not create any primary instruction in this context.

llvm/test/tools/llvm-snippy/codegen/rvv-no-available-instrs.yaml

@@ -25,4 +25,4 @@ sections:
 histogram:
     - [VSEXT_VF8, 1.0]
 
-# CHECK: We can not create any primary instruction in this context.
+# CHECK: error: We can not create any primary instruction in this context.

llvm/test/tools/llvm-snippy/rvv-config-biased/conf-all.yaml

@@ -52,7 +52,7 @@ histogram:
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:  - VM Selection Rules:
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-FULL-VLMAX1-DISABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-FULL-VLMAX1-DISABLED:  - Configuration Bag Listing:
 # CHECK-FULL-VLMAX1-DISABLED-COUNT-704:   /MaxVL
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:  - Configuration Bag Size: 704
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:  - State Cardinality: 15104 ~ {MASKS}
@@ -69,7 +69,7 @@ histogram:
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:  - VM Selection Rules:
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-FULL-VLMAX1-ENABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-FULL-VLMAX1-ENABLED:  - Configuration Bag Listing:
 # CHECK-FULL-VLMAX1-ENABLED-COUNT-800:   /MaxVL
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:  - Configuration Bag Size: 800
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:  - State Cardinality: 15200 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-biased/conf-nonsimplified.yaml

@@ -47,7 +47,7 @@ histogram:
 # CHECK-DEFAULT-NEXT:   - VM Selection Rules:
 # CHECK-DEFAULT-NEXT:     P: 0.66667 <all_ones>
 # CHECK-DEFAULT-NEXT:     P: 0.33333 <any_legal>
-# CHECK-DEFAULT-NEXT:  - Configuration Bag Listing:
+# CHECK-DEFAULT:  - Configuration Bag Listing:
 # CHECK-DEFAULT-NEXT:    P: 1 Conf: { e8, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 32768
 # CHECK-DEFAULT-NEXT:  - Configuration Bag Size: 1
 # CHECK-DEFAULT-NEXT:  - State Cardinality: 32768 ~ {MASKS}
@@ -65,7 +65,7 @@ histogram:
 # CHECK-VLEN512-NEXT:  - VM Selection Rules:
 # CHECK-VLEN512-NEXT:    P: 0.66667 <all_ones>
 # CHECK-VLEN512-NEXT:    P: 0.33333 <any_legal>
-# CHECK-VLEN512-NEXT:  - Configuration Bag Listing:
+# CHECK-VLEN512:  - Configuration Bag Listing:
 # CHECK-VLEN512-NEXT:    P: 1 Conf: { e8, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 256
 # CHECK-VLEN512-NEXT:  - Configuration Bag Size: 1
 # CHECK-VLEN512-NEXT:  - State Cardinality: 256 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-biased/conf-sew64-lmul1.yaml

@@ -49,7 +49,7 @@ histogram:
 # CHECK-SEW64-NEXT:  - VM Selection Rules:
 # CHECK-SEW64-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW64-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW64-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW64:  - Configuration Bag Listing:
 # CHECK-SEW64-NEXT:    P: 1 Conf: { e64, m1, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 2
 # CHECK-SEW64-NEXT:  - Configuration Bag Size: 1
 # CHECK-SEW64-NEXT:  - State Cardinality: 2 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-biased/conf-sew64-lmulX.yaml

@@ -50,7 +50,7 @@ histogram:
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:  - VM Selection Rules:
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW64-LMULX-VLMAX1-DISABLED:  - Configuration Bag Listing:
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.25 Conf: { e64, m1, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 2
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.25 Conf: { e64, m2, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 4
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.25 Conf: { e64, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 8
@@ -70,7 +70,7 @@ histogram:
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:  - VM Selection Rules:
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW64-LMULX-VLMAX1-ENABLED:  - Configuration Bag Listing:
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.22222 Conf: { e64, m1, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 2
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.22222 Conf: { e64, m2, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 4
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.22222 Conf: { e64, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 8

llvm/test/tools/llvm-snippy/rvv-config-biased/conf-sew8-lmul4.yaml

@@ -54,7 +54,7 @@ histogram:
 # CHECK-SEW8-NEXT:  - VM Selection Rules:
 # CHECK-SEW8-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW8-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW8-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW8:  - Configuration Bag Listing:
 # CHECK-SEW8-NEXT:    P: 1 Conf: { e8, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 64
 # CHECK-SEW8-NEXT:  - Configuration Bag Size: 1
 # CHECK-SEW8-NEXT:  - State Cardinality: 64 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-biased/conf-vill.yaml

@@ -85,7 +85,7 @@ histogram:
 # CHECK-BOTH-CONFIGS-NEXT:  - VM Selection Rules:
 # CHECK-BOTH-CONFIGS-NEXT:    P: 0.5 <all_ones>
 # CHECK-BOTH-CONFIGS-NEXT:    P: 0.5 <any_legal>
-# CHECK-BOTH-CONFIGS-NEXT:  - Configuration Bag Listing:
+# CHECK-BOTH-CONFIGS:  - Configuration Bag Listing:
 # CHECK-BOTH-CONFIGS-COUNT-704:   /MaxVL
 # CHECK-BOTH-CONFIGS-NEXT:    P: 0.5 Conf: {  Illegal Configurations:  1344 points }/MaxVL: 0
 # CHECK-BOTH-CONFIGS-NEXT:  - Configuration Bag Size: 2048
@@ -103,7 +103,7 @@ histogram:
 # CHECK-ILLEGAL-ONLY-NEXT:  - VM Selection Rules:
 # CHECK-ILLEGAL-ONLY-NEXT:    P: 0.5 <all_ones>
 # CHECK-ILLEGAL-ONLY-NEXT:    P: 0.5 <any_legal>
-# CHECK-ILLEGAL-ONLY-NEXT:  - Configuration Bag Listing:
+# CHECK-ILLEGAL-ONLY:  - Configuration Bag Listing:
 # CHECK-ILLEGAL-ONLY-NEXT:    P: 1 Conf: {  Illegal Configurations:  1344 points }/MaxVL: 0
 # CHECK-ILLEGAL-ONLY-NEXT:  - Configuration Bag Size: 1344
 # CHECK-ILLEGAL-ONLY-NEXT:  - State Cardinality: 0 ~ {MASKS}
@@ -120,7 +120,7 @@ histogram:
 # CHECK-LEGAL-ONLY-NEXT:  - VM Selection Rules:
 # CHECK-LEGAL-ONLY-NEXT:    P: 0.5 <all_ones>
 # CHECK-LEGAL-ONLY-NEXT:    P: 0.5 <any_legal>
-# CHECK-LEGAL-ONLY-NEXT:  - Configuration Bag Listing:
+# CHECK-LEGAL-ONLY:  - Configuration Bag Listing:
 # CHECK-LEGAL-ONLY-COUNT-704:   /MaxVL
 # CHECK-LEGAL-ONLY-NEXT:  - Configuration Bag Size: 704
 # CHECK-LEGAL-ONLY-NEXT:  - State Cardinality: 15104 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-biased/err-wrong-pvill.yaml

@@ -33,4 +33,4 @@ histogram:
     - [VXOR_VX, 1.0]
     - [VZEXT_VF4, 1.0]
 
-# CHECK: error: riscv-vector-vlvm::Pvill should be from [0.0;1.0]
+# CHECK: error: riscv-vector-unit: Pvill probability should be from [0.0;1.0]

llvm/test/tools/llvm-snippy/rvv-config-histogram/conf-all.yaml

@@ -54,7 +54,7 @@ histogram:
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:  - VM Selection Rules:
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-FULL-VLMAX1-DISABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-FULL-VLMAX1-DISABLED:  - Configuration Bag Listing:
 # CHECK-FULL-VLMAX1-DISABLED-COUNT-704:   /MaxVL
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:  - Configuration Bag Size: 704
 # CHECK-FULL-VLMAX1-DISABLED-NEXT:  - State Cardinality: 15104 ~ {MASKS}
@@ -71,7 +71,7 @@ histogram:
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:  - VM Selection Rules:
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-FULL-VLMAX1-ENABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-FULL-VLMAX1-ENABLED:  - Configuration Bag Listing:
 # CHECK-FULL-VLMAX1-ENABLED-COUNT-800:   /MaxVL
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:  - Configuration Bag Size: 800
 # CHECK-FULL-VLMAX1-ENABLED-NEXT:  - State Cardinality: 15200 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-histogram/conf-sew64-lmul1.yaml

@@ -52,7 +52,7 @@ histogram:
 # CHECK-SEW64-NEXT:  - VM Selection Rules:
 # CHECK-SEW64-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW64-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW64-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW64:  - Configuration Bag Listing:
 # CHECK-SEW64-NEXT:    P: 1 Conf: { e64, m1, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 2
 # CHECK-SEW64-NEXT:  - Configuration Bag Size: 1
 # CHECK-SEW64-NEXT:  - State Cardinality: 2 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-histogram/conf-sew64-lmulX.yaml

@@ -53,7 +53,7 @@ histogram:
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:  - VM Selection Rules:
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW64-LMULX-VLMAX1-DISABLED:  - Configuration Bag Listing:
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.25 Conf: { e64, m1, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 2
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.25 Conf: { e64, m2, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 4
 # CHECK-SEW64-LMULX-VLMAX1-DISABLED-NEXT:    P: 0.25 Conf: { e64, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 8
@@ -73,7 +73,7 @@ histogram:
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:  - VM Selection Rules:
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW64-LMULX-VLMAX1-ENABLED:  - Configuration Bag Listing:
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.22222 Conf: { e64, m1, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 2
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.22222 Conf: { e64, m2, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 4
 # CHECK-SEW64-LMULX-VLMAX1-ENABLED-NEXT:    P: 0.22222 Conf: { e64, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 8

llvm/test/tools/llvm-snippy/rvv-config-histogram/conf-sew8-lmul4.yaml

@@ -52,7 +52,7 @@ histogram:
 # CHECK-SEW8-NEXT:  - VM Selection Rules:
 # CHECK-SEW8-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW8-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW8-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW8:  - Configuration Bag Listing:
 # CHECK-SEW8-NEXT:    P: 1 Conf: { e8, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 64
 # CHECK-SEW8-NEXT:  - Configuration Bag Size: 1
 # CHECK-SEW8-NEXT:  - State Cardinality: 64 ~ {MASKS}

llvm/test/tools/llvm-snippy/rvv-config-histogram/conf-vlsetivli-limits.yaml

@@ -42,7 +42,7 @@ histogram:
 # CHECK-SEW8-NEXT:  - VM Selection Rules:
 # CHECK-SEW8-NEXT:    P: 0.66667 <all_ones>
 # CHECK-SEW8-NEXT:    P: 0.33333 <any_legal>
-# CHECK-SEW8-NEXT:  - Configuration Bag Listing:
+# CHECK-SEW8:  - Configuration Bag Listing:
 # CHECK-SEW8-NEXT:    P: 1 Conf: { e8, m4, tu, mu, vxsat: 0, vxrm: rnu }/MaxVL: 64
 # CHECK-SEW8-NEXT:  - Configuration Bag Size: 1
 # CHECK-SEW8-NEXT:  - State Cardinality: 64 ~ {MASKS}

llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.cpp

@@ -220,6 +220,7 @@ struct RVVConfigurationSpace {
   BiasGuides Guides;
   RVVUnitInfo VUInfo;
 
+  static constexpr auto kUnitName = "riscv-vector-unit";
   static void mapYaml(llvm::yaml::IO &IO,
                       std::optional<RVVConfigurationSpace> &CS);
 };
@@ -656,7 +657,7 @@ template <> struct GeneratorFactory<RVVConfigurationInfo::VMGeneratorHolder> {
 void RVVConfigurationSpace::mapYaml(llvm::yaml::IO &IO,
                                     std::optional<RVVConfigurationSpace> &CS) {
   yaml::EmptyContext Ctx;
-  IO.mapOptionalWithContext("riscv-vector-unit", CS, Ctx);
+  IO.mapOptionalWithContext(RVVConfigurationSpace::kUnitName, CS, Ctx);
 }
 
 class RVVConfig : public RVVConfigInterface {
@@ -762,20 +763,30 @@ template <> struct yaml::MappingTraits<RVVUnitInfo> {
   }
 };
 
+static bool isCorrectProbability(double Prob) {
+  return Prob >= 0.0 && Prob <= 1.0;
+}
+
 template <> struct yaml::MappingTraits<BiasGuides> {
+  static constexpr auto kProbBounds = "probability should be from [0.0;1.0]";
+
   static void mapping(yaml::IO &IO, BiasGuides &Guides) {
     Guides.Enabled = true;
     IO.mapRequired("P", Guides.ModeChangeP);
+    IO.mapOptional("Pvill", Guides.SetVillP);
+  }
 
+  static std::string validate(yaml::IO &IO, BiasGuides &Guides) {
     // TODO: implemenent alternative mode changing schemes and
     // replace probability with weight
-    if (!(Guides.ModeChangeP >= 0.0 && Guides.ModeChangeP <= 1.0))
-      snippy::fatal("riscv-vector-vlvm::P should be from [0.0;1.0]");
-
-    IO.mapOptional("Pvill", Guides.SetVillP);
-
-    if (!(Guides.SetVillP >= 0.0 && Guides.SetVillP <= 1.0))
-      snippy::fatal("riscv-vector-vlvm::Pvill should be from [0.0;1.0]");
+    if (!isCorrectProbability(Guides.ModeChangeP))
+      return std::string(RVVConfigurationSpace::kUnitName) + ": P " +
+             kProbBounds;
+
+    if (!isCorrectProbability(Guides.SetVillP))
+      return std::string(RVVConfigurationSpace::kUnitName) + ": Pvill " +
+             kProbBounds;
+    return {};
   }
 };
 
@@ -788,7 +799,7 @@ template <> struct yaml::MappingTraits<RVVConfigurationSpace> {
 
 template <> struct yaml::MappingTraits<VectorUnitRules> {
   static void mapping(yaml::IO &IO, VectorUnitRules &VU) {
-    IO.mapRequired("riscv-vector-unit", VU.Config);
+    IO.mapRequired(RVVConfigurationSpace::kUnitName, VU.Config);
   }
 };
 
@@ -818,12 +829,11 @@ unsigned computeVLMax(unsigned VLEN, unsigned SEW, RISCVII::VLMUL LMUL) {
 
 std::pair<unsigned, bool> computeDecodedEMUL(unsigned SEW, unsigned EEW,
                                              RISCVII::VLMUL LMUL) {
-  if (isReservedValues(SEW, LMUL) || !isLegalSEW(SEW)) {
+  if (isReservedValues(SEW, LMUL) || !isLegalSEW(SEW) || !isLegalSEW(EEW)) {
     // Calculating EMUL doesn't make sense for illegal values of SEW or LMUL, so
     // just return {1, 0}
     return {1, 0};
   }
-  assert(isLegalSEW(EEW));
 
   auto [Multiplier, IsFractional] = RISCVVType::decodeVLMUL(LMUL);
   unsigned long long Dividend = EEW * (IsFractional ? 1u : Multiplier);
@@ -1264,6 +1274,7 @@ void RVVConfigurationInfo::print(raw_ostream &OS) const {
     OS << "P: " << floatToString(Prob, 5) << " ";
     OS << "<" << Gen->identify() << ">\n";
   }
+
   OS << "  - Configuration Bag Listing:\n";
   unsigned IllegalPointsSize = 0;
   for (const auto &[Point, Prob] :

llvm/tools/llvm-snippy/lib/Target/RISCV/RVVUnitConfig.h

@@ -52,6 +52,8 @@ std::unique_ptr<RVVConfigInterface> createRVVConfig();
 
 // Compute EMUL = EEW / SEW * LMUL
 RISCVII::VLMUL computeEMUL(unsigned SEW, unsigned EEW, RISCVII::VLMUL LMUL);
+std::pair<unsigned, bool> computeDecodedEMUL(unsigned SEW, unsigned EEW,
+                                             RISCVII::VLMUL LMUL);
 bool isValidEMUL(unsigned SEW, unsigned EEW, RISCVII::VLMUL LMUL);
 
 inline static bool canBeEncoded(unsigned SEW) {
@@ -228,6 +230,10 @@ struct RVVConfigurationInfo final {
   bool isModeChangeArtificial() const { return ArtificialModeChange; }
   const ModeChangeInfo &getModeChangeInfo() const { return SwitchInfo; }
 
+  const std::vector<RVVConfiguration> &getConfigs() const {
+    return CfgGen.elements();
+  }
+
   void print(raw_ostream &OS) const;
   void dump() const;
 
@@ -238,7 +244,6 @@ struct RVVConfigurationInfo final {
   using ConfigGenerator = DiscreteGeneratorInfo<RVVConfiguration>;
   using VLGenerator = DiscreteGeneratorInfo<VLGeneratorHolder>;
   using VMGenerator = DiscreteGeneratorInfo<VMGeneratorHolder>;
-  using ModeGenerator = DiscreteGeneratorInfo<int>;
 
   RVVConfigurationInfo(unsigned VLEN, ConfigGenerator &&CfgGen,
                        VLGenerator &&VLGen, VMGenerator &&VMGen,

llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp

@@ -399,12 +399,11 @@ static RegStorageType regToStorage(Register Reg) {
   return RegStorageType::VReg;
 }
 
-static bool isLegalRVVInstr(unsigned Opcode, const MachineBasicBlock &MBB,
+static bool isLegalRVVInstr(unsigned Opcode, const RVVConfiguration &Cfg,
+                            unsigned VL, unsigned VLEN,
                             const GeneratorContext &GC) {
-  auto &RISCVCtx = GC.getTargetContext().getImpl<RISCVGeneratorContext>();
   if (!isRVV(Opcode))
     return false;
-  auto &Cfg = RISCVCtx.getCurrentRVVCfg(MBB);
   auto SEW = Cfg.SEW;
   auto LMUL = Cfg.LMUL;
 
@@ -806,6 +805,16 @@ breakDownAddrForInstrWithImmOffset(AddressInfo AddrInfo, const MachineInstr &MI,
 
 using OpcodeFilter = GeneratorContext::OpcodeFilter;
 
+static OpcodeFilter getRVVDefaultPolicyFilterImpl(const RVVConfiguration &Cfg,
+                                                  unsigned VL, unsigned VLEN,
+                                                  const GeneratorContext &GC) {
+  return [&Cfg, VL, VLEN, &GC](unsigned Opcode) {
+    if (!isRVV(Opcode))
+      return true;
+    return isLegalRVVInstr(Opcode, Cfg, VL, VLEN, GC);
+  };
+}
+
 static OpcodeFilter getDefaultPolicyFilterImpl(const MachineBasicBlock &MBB,
                                                const GeneratorContext &GC) {
   auto &RISCVCtx = GC.getTargetContext().getImpl<RISCVGeneratorContext>();
@@ -816,11 +825,11 @@ static OpcodeFilter getDefaultPolicyFilterImpl(const MachineBasicBlock &MBB,
       return true;
     };
 
-  return [&GC, &MBB](unsigned Opcode) {
-    if (isRVV(Opcode) && !isLegalRVVInstr(Opcode, MBB, GC))
-      return false;
-    return true;
-  };
+  const auto &Cfg = RISCVCtx.getCurrentRVVCfg(MBB);
+  auto VL = RISCVCtx.getVL(MBB);
+  auto VLEN = RISCVCtx.getVLEN();
+
+  return getRVVDefaultPolicyFilterImpl(Cfg, VL, VLEN, GC);
 }
 
 inline bool checkSupportedOrdering(const OpcodeHistogram &H) {
@@ -3247,7 +3256,7 @@ void SnippyRISCVTarget::rvvGenerateModeSwitchAndUpdateContext(
   // Also in this case, the already selected NewVLVM.VL has a value exceeding
   // the maximum possible for this instruction (due to its encoding), so we
   // reselect the NewVLVM.VL, taking into account its possible values for
-  // VSEIVLI.
+  // VSETIVLI.
   if (NewVLVM.VL > kMaxVLForVSETIVLI &&
       (ModeChangeInfo.WeightVSETVL + ModeChangeInfo.WeightVSETVLI) <
           std::numeric_limits<double>::epsilon())
@@ -3484,17 +3493,20 @@ static void dumpRvvConfigurationInfo(StringRef FilePath,
 std::unique_ptr<TargetGenContextInterface>
 SnippyRISCVTarget::createTargetContext(const GeneratorContext &Ctx) const {
   auto RISCVCfg = RISCVConfigurationInfo::constructConfiguration(Ctx);
-  bool IsRVVPresent = RISCVCfg.getVUConfig().getModeChangeInfo().RVVPresent;
-  bool IsApplyValuegramEachInst =
-      Ctx.getGenSettings().Cfg.RegsHistograms.has_value();
-  if (IsRVVPresent && IsApplyValuegramEachInst)
-    snippy::fatal("Not implemented", "vector registers can't be initialized");
+  auto RGC = std::make_unique<RISCVGeneratorContext>(std::move(RISCVCfg));
+  const auto &VUInfo = RGC->getVUConfigInfo();
+  bool IsRVVPresent = VUInfo.getModeChangeInfo().RVVPresent;
+  if (IsRVVPresent) {
+    bool IsApplyValuegramEachInst =
+        Ctx.getGenSettings().Cfg.RegsHistograms.has_value();
+    if (IsApplyValuegramEachInst)
+      snippy::fatal("Not implemented", "vector registers can't be initialized");
+  }
 
   if (DumpRVVConfigurationInfo.isSpecified())
-    dumpRvvConfigurationInfo(DumpRVVConfigurationInfo.getValue(),
-                             RISCVCfg.getVUConfig());
+    dumpRvvConfigurationInfo(DumpRVVConfigurationInfo.getValue(), VUInfo);
 
-  return std::make_unique<RISCVGeneratorContext>(std::move(RISCVCfg));
+  return std::move(RGC);
 }
 
 std::unique_ptr<TargetConfigInterface>