Merge pull request favalex#19 from grzegorzheldt/master

Adding silent flag

bin/modbus

@@ -77,6 +77,7 @@ def main():
     parser.add_argument('-p', '--stop-bits', type=int, default=1)
     parser.add_argument('-P', '--parity', choices=['e', 'o', 'n'], default='n')
     parser.add_argument('-v', '--verbose', action='store_true')
+    parser.add_argument('-S', '--silent', action='store_true')
     parser.add_argument('-t', '--timeout', type=float, default=5.0)
     parser.add_argument('-B', '--byte-order', choices=['le', 'be', 'mixed'], default='be')
     parser.add_argument('device')
@@ -96,10 +97,10 @@ def main():
         ch = ColourHandler()
         mainLogger.addHandler(ch)
 
-        definitions = Definitions()
+        definitions = Definitions(args.silent)
         definitions.parse(args.registers + os.environ.get('MODBUS_DEFINITIONS', '').split(':'))
 
-        connect_to_device(args).perform_accesses(parse_accesses(args.access, definitions, args.byte_order), definitions).close()
+        connect_to_device(args).perform_accesses(parse_accesses(args.access, definitions, args.byte_order, args.silent), definitions).close()
 
     finally:
         # restore stdout/stderr if colorama has modified them (mostly on windows)

modbus_cli/access.py

@@ -21,14 +21,15 @@ def dump(xs):
 
 
 class Access:
-    def __init__(self, modbus_type, addresses, pack_types, values=None, names=None, presenters=None, byte_order='be'):
+    def __init__(self, modbus_type, addresses, pack_types, values=None, names=None, presenters=None, byte_order='be', silent=False):
         self.modbus_type = modbus_type
         self.values_to_write = values or [None] * len(addresses)
         self.addresses = addresses
         self.pack_types = pack_types
         self.names = names or [None] * len(addresses)
         self.presenters = presenters or [None] * len(addresses)
         self.byte_order = byte_order
+        self.silent = silent
 
     def address(self):
         return self.addresses[0]
@@ -80,7 +81,10 @@ def print_values(self, definitions=None):
         for label, value, presenter in zip(self.labels(), self.values, self.presenters):
             if len(value) == 1:
                 value = value[0]
-            logging.info('{}: {} {}'.format(label, value, self.present_value(value, presenter, definitions)))
+            if self.silent:
+                logging.info('{}'.format(value))
+            else:
+                logging.info('{}: {} {}'.format(label, value, self.present_value(value, presenter, definitions)))
 
     def present_value(self, value, presenter, definitions):
         if type(value) != int:
@@ -254,7 +258,7 @@ def group_accesses(accesses):
     return grouped
 
 
-def parse_access(register, name, write, value, byte_order):
+def parse_access(register, name, write, value, byte_order, silent):
     modbus_type, address, pack_type, presenter = re.match(REGISTER_RE, register).groups()
 
     if not address:
@@ -288,10 +292,10 @@ def parse_access(register, name, write, value, byte_order):
         raise ValueError("Invalid Modbus type '{}'. Only coils and holding registers are writable".format(modbus_type))
 
     return Access(modbus_type, [address], [pack_type], [value],
-                  names=[name], presenters=[presenter], byte_order=byte_order)
+                  names=[name], presenters=[presenter], byte_order=byte_order, silent=silent)
 
 
-def parse_accesses(s, definitions, byte_order='be'):
+def parse_accesses(s, definitions, byte_order='be', silent=False):
     accesses = []
 
     for access in s:
@@ -305,14 +309,14 @@ def parse_accesses(s, definitions, byte_order='be'):
             write = True
 
         if re.fullmatch(REGISTER_RE, register):
-            access = parse_access(register, None, write, value, byte_order)
+            access = parse_access(register, None, write, value, byte_order, silent)
             if access:
                 accesses.append(access)
         else:
             register_re = re.compile(fnmatch.translate(register))
             for name, definition in definitions.registers.items():
                 if register_re.match(name):
-                    access = parse_access(definition, name, write, value, byte_order)
+                    access = parse_access(definition, name, write, value, byte_order, silent)
                     if access:
                         accesses.append(access)
 

modbus_cli/definitions.py

@@ -5,9 +5,10 @@
 
 
 class Definitions:
-    def __init__(self):
+    def __init__(self, silent):
         self.registers = {}
         self.presenters = {}
+        self.silent = silent
 
     def parse(self, filenames):
         for filename in filenames:
@@ -24,7 +25,8 @@ def parse(self, filenames):
                             self.parse_line(accumulated_line)
                             accumulated_line = line
                     self.parse_line(accumulated_line)
-        logging.info('Parsed %d registers definitions from %d files', len(self.registers), len(filenames))
+        if not self.silent: 
+            logging.info('Parsed %d registers definitions from %d files', len(self.registers), len(filenames))
 
     def parse_line(self, line):
         if not line:

tests/test_definitions.py

@@ -9,7 +9,13 @@
 class TestDefinitions(unittest.TestCase):
 
     def test_parse(self):
-        it = Definitions()
+        it = Definitions(False)
+        it.parse(['tests/simple.modbus'])
+        self.assertEqual({'a_register': 'i@100/4H:a_presenter'}, it.registers)
+        self.assertEqual({':a_presenter': {0: 'x', 1: 'y'}}, it.presenters)
+
+    def test_parse_silent(self):
+        it = Definitions(True)
         it.parse(['tests/simple.modbus'])
         self.assertEqual({'a_register': 'i@100/4H:a_presenter'}, it.registers)
         self.assertEqual({':a_presenter': {0: 'x', 1: 'y'}}, it.presenters)