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An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…
Use Xilinx RTL Wizard flow to run program on the SoC PULPino
Peripheral access API for RI5CY core of RV32M1 SoC
Pulpino fork + integration with ibex_ppu_pv1
cv32e40p RTL description: each branch is a version of a protected cv32e40p core
Simulation and Synthesis on FPGA of SoC with IBEX or CV32E40P
This is a repo holding notes about the CV32E40P processor.
implementação do core CV32E40P da plataforma PULP
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
An open-source microcontroller system based on RISC-V
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core
This is made as a part of RISC-V Hackathon on the Topic FLOATING POINT which includes designing the square root and parameterized matrix multiplication on the Single precision float point inputs.
National RISC-V student contest CV32A6
This repository is focused on cybersecurity in the industrial world. Many industrial communication protocols and equipment is investigated and pentested
Named Data Networking and Modbus-TCP Water Treatment Simulation Testbed
This is an industrial dataset contains eight different types of ICS protocols, mainly collected for the evaluation of protocol reverse engineering tools. We hope it can be supplemented in the future.
Tools, tips, tricks, and more for exploring ICS Security.
NetPlier: Probabilistic Network Protocol Reverse Engineering from Message Traces