Merge all the extended raw instructions

riscv-isa-sim/riscv/decode.h

@@ -140,11 +140,16 @@ class regfile_t
 #define READ_XBREG(reg) STATE.XBR[reg]
 #define EXT1 READ_XBREG(insn.rs1())
 #define EXT2 READ_XBREG(insn.rs2())
+#define EXT3 READ_XBREG(insn.rd())
+#define RD READ_REG(insn.rd())
 
 #define READ_FREG(reg) STATE.FPR[reg]
 #define RS1 READ_REG(insn.rs1())
 #define RS2 READ_REG(insn.rs2())
 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
+// xbgas extended instruction support
+# define WRITE_REG_EXD(reg, value) STATE.XBR.write(reg, value)
+#define WRITE_EXD(value) WRITE_REG_EXD(insn.rd(), value)
 
 #ifndef RISCV_ENABLE_COMMITLOG
 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)

riscv-isa-sim/riscv/insns/eaddi.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(EXT1 + insn.i_imm());

riscv-isa-sim/riscv/insns/eaddie.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_EXD(RS1 + insn.i_imm());

riscv-isa-sim/riscv/insns/eaddix.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_EXD(EXT1 + insn.i_imm());

riscv-isa-sim/riscv/insns/erlb.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.xbgas_load_int8(EXT2, RS1));

riscv-isa-sim/riscv/insns/erlbu.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.xbgas_load_uint8(EXT2, RS1));

riscv-isa-sim/riscv/insns/erld.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.xbgas_load_int64(EXT2, RS1));

riscv-isa-sim/riscv/insns/erle.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_EXD(MMU.xbgas_load_int64(EXT2, RS1));

riscv-isa-sim/riscv/insns/erlh.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.xbgas_load_int16(EXT2, RS1));

riscv-isa-sim/riscv/insns/erlhu.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.xbgas_load_uint16(EXT2, RS1));

riscv-isa-sim/riscv/insns/erlw.h

@@ -0,0 +1,2 @@
+require_rv64;
+WRITE_RD(MMU.xbgas_load_int32(EXT2, RS1));

riscv-isa-sim/riscv/insns/ersb.h

@@ -0,0 +1,2 @@
+require_rv64;
+MMU.xbgas_store_uint8(EXT2, RS1, RD);

riscv-isa-sim/riscv/insns/ersd.h

@@ -0,0 +1,9 @@
+require_rv64;
+#ifdef DEBUG
+int i;
+for(i = 0; i< 32; i++){
+	if(READ_XBREG(i))
+		std::cout << "\nDEBUG::  e" <<std::dec<<i<<" = "<< READ_XBREG(i);
+}
+#endif
+MMU.xbgas_store_uint64(EXT2, RS1, RD);

riscv-isa-sim/riscv/insns/erse.h

@@ -0,0 +1,2 @@
+require_rv64;
+MMU.xbgas_store_uint64(EXT2,RS1,EXT3);

riscv-isa-sim/riscv/insns/ersh.h

@@ -0,0 +1,2 @@
+require_rv64;
+MMU.xbgas_store_uint16(EXT2, RS1, RD);

riscv-isa-sim/riscv/insns/ersw.h

@@ -0,0 +1,2 @@
+require_rv64;
+MMU.xbgas_store_uint32(EXT2, RS1, RD);

riscv-isa-sim/riscv/mmu.cc

@@ -4,6 +4,7 @@
 #include "sim.h"
 #include "processor.h"
 #include <mpi.h>
+#include <iostream>
 //#define DEBUG
 mmu_t::mmu_t(sim_t* sim, processor_t* proc)
  : sim(sim), proc(proc),
@@ -98,6 +99,10 @@ reg_t reg_from_bytes(size_t len, const uint8_t* bytes)
 
 void mmu_t::store_remote_path(int64_t target, reg_t addr, reg_t len,uint8_t* bytes )
 {
+
+#ifdef DEBUG
+	std::cout << "DEBUG::  Target ID = " << target << " Local Addr = " << addr << " value = " << std::dec<<(uint64_t)(*bytes) << std::endl;
+#endif
 	int rank	=	sim->myid;
 	// Temporarily go through the MMU address translation
   reg_t paddr = translate(addr, STORE);

riscv-isa-sim/riscv/mmu.h

@@ -126,13 +126,9 @@ class mmu_t
   load_func(int128)
 
 
-				//if(unlikely( std::to_string(#type) == "int128"))\
-					std::runtime_error("Local 128b integer load is not supported\n");\
-				else{\
   // template for functions that load an aligned value from remote meemory devices
   #define xbgas_load_func(type) \
     inline type##_t xbgas_load_##type(reg_t upper, reg_t lower) { \
-	  std::cout <<"DEBUG::  The "<< "xbgas_load_" <<#type<<" are executed successfully\n";\
 		  upper = 1;\
 			if (!upper)\
 					load_##type(lower);\
@@ -141,6 +137,7 @@ class mmu_t
 				throw std::runtime_error("The extended address:" + std::to_string(upper) + "does not match any remote node");\
       type##_t res; \
       load_remote_path(target, lower, sizeof(type##_t), (uint8_t*)&res); \
+	    std::cout <<"DEBUG::  The "<< "xbgas_load_" <<#type<<" are executed successfully\n";\
       return res; \
     }
 
@@ -186,17 +183,20 @@ class mmu_t
 	store_func(uint128) 
 
 
-
+		  //std::cout << "\nupper = " << upper << " addr = " << std::hex << addr <<std::endl;
+		  //std::cout << "\nvalue = " << std::dec<<(uint64_t)val << std::endl;
+			//std::cout << " value = " << val << std::endl;	
+			//upper = 1;
 	// template for functions that store an aligned value to memory
   #define xbgas_store_func(type) \
     void xbgas_store_##type(reg_t upper, reg_t addr, type##_t val) { \
-			upper = 1;\
 			if(!upper)\
 				return store_##type(addr, val);\
 			int64_t target = sim->olb_visit(upper);\
 			if (unlikely(target == -1))\
 				throw std::runtime_error("The extended address:" + std::to_string(upper) + "does not match any remote node");\
 			store_remote_path(target, addr, sizeof(type##_t), (uint8_t*)&val); \
+	    std::cout <<"DEBUG::  The "<< "xbgas_store_" <<#type<<" are executed successfully\n";\
     }
 
 

riscv-isa-sim/riscv/riscv.mk.in

@@ -267,6 +267,22 @@ riscv_insn_list = \
 	esw\
 	esh\
 	ese\
+	erld\
+	erlw\
+	erlh\
+	erlhu\
+	erlb\
+	erlbu\
+	erle\
+	ersd\
+	ersw\
+	ersh\
+	ersb\
+	erse\
+	eaddi\
+	eaddie\
+	eaddix\
+
 
 riscv_gen_srcs = \
 	$(addsuffix .cc,$(riscv_insn_list))

riscv-isa-sim/spike_main/disasm.cc

@@ -43,6 +43,24 @@ struct : public arg_t {
   }
 } xrs2;
 
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xbr_name[insn.rd()];
+  }
+} erd;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xbr_name[insn.rs1()];
+  }
+} ers1;
+
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return xbr_name[insn.rs2()];
+  }
+} ers2;
+
 struct : public arg_t {
   std::string to_string(insn_t insn) const {
     return fpr_name[insn.rd()];