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Commits on Apr 1, 2016

• AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}

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  059753c

Commits on Mar 30, 2016

• AMDGPU/SI: Improve MachineSchedModel definition

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• AMDGPU/SI: Enable lanemask tracking in misched

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Commits on Mar 28, 2016

• AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructions

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Commits on Mar 24, 2016

• AMDGPU/SI: Add Polaris support

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Commits on Mar 23, 2016

• AMDGPU: Cache information about register pressure sets

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Commits on Mar 21, 2016

• AMDGPU/SI: Fix threshold calculation for branching when exec is zero

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Commits on Mar 14, 2016

• AMDGPU/SI: Handle wait states required for DPP instructions

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Commits on Mar 9, 2016

• SelectionDAG: Fix a crash on inline asm when output register supports multiple types

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Commits on Mar 4, 2016

• AMDGPU/SI: Add support for spiling SGPRs to scratch buffer

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• AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserter

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Commits on Mar 3, 2016

• AMDGPU: Insert two S_NOP instructions for every high level source statement.

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• AMDGPU/SI: Don't try to move scratch wave offset when there are no free SGPRs

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Commits on Feb 22, 2016

• [AMDGPU][llvm-mc] Support for 32-bit inline literals

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• [AMDGPU] [llvm-mc] [VI] Fix encoding of LDS/GDS instructions.

  Show description for 52b2fdb
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• docs/AMDGPUUsage: Update assembly example

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Commits on Feb 20, 2016

• AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointer

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Commits on Feb 19, 2016

• AMDGPU/SI: Fix s_waitcnt insertion for flat instructions

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Commits on Feb 18, 2016

• [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target

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Commits on Feb 16, 2016

• [AMDGPU] Rename $dst operand to $vdst for VOP instructions.

  Show description for f4f96b9
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Commits on Feb 13, 2016

• AMDGPU/SI: Add llvm.amdgcn.mov.dpp intrinsic

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• AMDGPU/SI: Add instruction defs for VOP1 DPP instructions

  Show description for 61b6c32
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• AMDGPU/SI: Organize intrinsics by subtarget

  Show description for 20f44b5
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Commits on Feb 12, 2016

• AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions

  Show description for 98ef447
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• [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler

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Commits on Feb 11, 2016

• AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRs

  Show description for dfa41e5
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• AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist

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• [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing

  Show description for 0f13bd9
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• [AMDGPU] Assembler: Fix VOP3 only instructions

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Commits on Feb 10, 2016

• StructurizeCFG: Initialize SkipUniformRegions in the default constructor

  Show description for 8983a17
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• StructurizeCFG: Add an option for skipping regions with only uniform branches

  Show description for 7c9f178
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Commits on Feb 8, 2016

• AMDGPU/SI: Implement a work-around for smrd corrupting vccz bit

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Commits on Feb 5, 2016

• TableGen: Add IsOptional field to AsmOperandClass

  Show description for 25257d8
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• AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo

  Show description for d794d16
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• AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors

  Show description for 739e22c
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