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tejdabhankar/README.md

Hi 👋, I'm Tej Dabhankar

A passionate FPGA Developer and Digital Design Engineer from India

tejdabhankar

tejdabhankar

tejdabhankar

  • 🔭 I’m currently working on General purpose RISC-V CPU

  • 🌱 I’m currently learning Verilog and Computer Architecture.

  • 👯 I’m looking to collaborate on CPU

  • 📝 I regularly write articles on https://medium.com/@visionvlsi

  • 💬 Ask me about Computers Digital Circuits and SBC's

  • 📫 How to reach me tejasdabhankar

  • ⚡ Fun fact The best and worst thing I have is me.

Blogs posts

Connect with me:

tejdabhankar tejas dabhankar tejdabhankar @visionvlsi

Languages and Tools:

arduino cplusplus git linux python

tejdabhankar

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tejdabhankar

Pinned Loading

  1. 1_wire 1_wire Public

    Functional Implementaiton of 1 wire

    Verilog 1

  2. WS2812 WS2812 Public

    Verilog 1

  3. WS2812_Custom WS2812_Custom Public

    Verilog 1

  4. UART_Implementation UART_Implementation Public

    Verilog 1

  5. amba_apb amba_apb Public

    This repository has the rtl design of amba apb on verilog.

    Verilog