soc: nxp: Add RW SOC Family

Add SOC definition for NXP RW Family

Signed-off-by: Declan Snyder <[email protected]>

MAINTAINERS.yml

@@ -3332,6 +3332,7 @@ NXP Platforms (MCU):
     - soc/nxp/imxrt/
     - soc/nxp/kinetis/
     - soc/nxp/lpc/
+    - soc/nxp/rw/
     - dts/arm/nxp/
     - samples/boards/nxp*/
   files-regex-exclude:

drivers/clock_control/clock_control_mcux_syscon.c

@@ -158,9 +158,12 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
 #if defined(CONFIG_PWM_MCUX_SCTIMER)
 	case MCUX_SCTIMER_CLK:
 #endif
+
+#ifndef CONFIG_SOC_SERIES_RW6XX
 	case MCUX_BUS_CLK:
 		*rate = CLOCK_GetFreq(kCLOCK_BusClk);
 		break;
+#endif
 
 #if defined(CONFIG_I3C_MCUX)
 	case MCUX_I3C_CLK:

modules/Kconfig.mcux

@@ -6,7 +6,7 @@
 config HAS_MCUX
 	bool
 	depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \
-		SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT
+		SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW
 if HAS_MCUX
 
 config MCUX_CORE_SUFFIX

soc/nxp/rw/CMakeLists.txt

@@ -0,0 +1,13 @@
+# Copyright 2022-2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  flexspi_clock_setup.c
+  )
+
+zephyr_linker_sources_ifdef(CONFIG_NXP_RW6XX_BOOT_HEADER
+  ROM_START SORT_KEY 0 boot_header.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/nxp/rw/Kconfig

@@ -0,0 +1,87 @@
+# Copyright 2022-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RW6XX
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_CORTEX_M_HAS_DWT
+	select CLOCK_CONTROL
+	select PLATFORM_SPECIFIC_INIT
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select HAS_MCUX_OS_TIMER
+	select ARM_TRUSTZONE_M
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select HAS_MCUX
+	select HAS_MCUX_FLEXCOMM
+	select INIT_SYS_PLL
+	select HAS_MCUX_CACHE
+
+if SOC_SERIES_RW6XX
+
+config INIT_SYS_PLL
+	bool "Initialize SYS PLL"
+
+menuconfig NXP_RW6XX_BOOT_HEADER
+	bool "Create boot header"
+	default y
+	help
+	  Create data structures required by the boot ROM to boot the
+	  application from an external flash device.
+
+if NXP_RW6XX_BOOT_HEADER
+
+choice BOOT_DEVICE
+	prompt "Boot device selection"
+	default BOOT_FLEXSPI_NOR
+
+config BOOT_FLEXSPI_NOR
+	bool "FlexSPI serial NOR"
+
+endchoice
+
+config FLASH_CONFIG_OFFSET
+	hex "Flash config data offset"
+	default 0x400
+	help
+	  The flash config offset provides the boot ROM with the on-board
+	  flash type and parameters. The boot ROM requires a fixed flash conifg
+	  offset for FlexSPI device.
+
+config IMAGE_VECTOR_TABLE_OFFSET
+	hex "Image vector table offset"
+	default 0x1000
+	help
+	  The Image Vector Table (IVT) provides the boot ROM with pointers to
+	  the application entry point and device configuration data. The boot
+	  ROM requires a fixed IVT offset for each type of boot device.
+
+# Used for default value in FLASH_MCUX_FLEXSPI_XIP
+DT_CHOSEN_Z_FLASH := zephyr,flash
+DT_COMPAT_FLEXSPI := nxp,imx-flexspi
+# Macros to shorten Kconfig definitions
+DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
+DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
+
+config FLASH_MCUX_FLEXSPI_XIP
+	bool "MCUX FlexSPI flash access with xip"
+	default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
+	select XIP
+	help
+	  Allows for the soc to safely initialize the clocks for the
+	  FlexSpi when planning to execute code in FlexSpi Memory.
+
+config NXP_RW_ROM_RAMLOADER
+	depends on !FLASH_MCUX_FLEXSPI_XIP
+	# Required so that debugger will load image to correct offset
+	select BUILD_OUTPUT_HEX
+	bool "Create output image that RW ROM can load from FlexSPI to ram"
+	help
+	  Builds an output image that the RW BootROM can load from the
+	  FlexSPI boot device into RAM region. The image will be loaded
+	  from FLEXSPI into the region specified by `zephyr,flash` node.
+
+endif # NXP_RW6XX_BOOT_HEADER
+
+endif # SOC_SERIES_RW6XX

soc/nxp/rw/Kconfig.defconfig

@@ -0,0 +1,68 @@
+# Copyright 2022-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RW6XX
+
+config ROM_START_OFFSET
+	default 0x400 if BOOTLOADER_MCUBOOT
+	default 0x1300 if NXP_RW6XX_BOOT_HEADER
+
+config NUM_IRQS
+	default 129
+if CORTEX_M_SYSTICK
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 260000000
+
+endif # CORTEX_M_SYSTICK
+
+# The base address is determined from the zephyr,flash node with the following
+# precedence:
+# FlexSPI base address (if flash node is on a FlexSPI bus)
+# node reg property (used for memory regions such as SRAM)
+
+# Workaround for not being able to have commas in macro arguments
+
+DT_CHOSEN_Z_FLASH := zephyr,flash
+DT_COMPAT_FLEXSPI := nxp,imx-flexspi
+
+# Macros to shorten Kconfig definitions
+DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
+DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
+
+config FLASH_BASE_ADDRESS
+	default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
+		if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+# The RW6xx has no internal flash. If the flash node has a size property,
+# use that over the reg property. This is used for the external flash
+# present on the board. Otherwise, fallback to the reg property
+config FLASH_SIZE
+	default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
+		if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+if NXP_RW_ROM_RAMLOADER
+
+FLASH_BASE := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1)
+config BUILD_OUTPUT_ADJUST_LMA
+	default "$(FLEXSPI_BASE) - $(FLASH_BASE)"
+
+endif # NXP_RW_ROM_RAMLOADER
+
+if FLASH_MCUX_FLEXSPI_XIP
+
+# Avoid RWW hazards by defaulting logging to disabled
+choice FLASH_LOG_LEVEL_CHOICE
+	default FLASH_LOG_LEVEL_OFF
+endchoice
+
+choice MEMC_LOG_LEVEL_CHOICE
+	default MEMC_LOG_LEVEL_OFF
+endchoice
+
+endif # FLASH_MCUX_FLEXSPI_XIP
+
+endif # SOC_SERIES_RW6XX

soc/nxp/rw/Kconfig.soc

@@ -0,0 +1,60 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_NXP_RW
+	bool
+
+config SOC_FAMILY
+	default "nxp_rw" if SOC_FAMILY_NXP_RW
+
+config SOC_SERIES_RW6XX
+	bool
+	select SOC_FAMILY_NXP_RW
+
+config SOC_SERIES
+	default "rw6xx" if SOC_SERIES_RW6XX
+
+config SOC_RW610
+	bool
+	select SOC_SERIES_RW6XX
+
+config SOC_RW612
+	bool
+	select SOC_SERIES_RW6XX
+
+config SOC
+	default "rw610" if SOC_RW610
+	default "rw612" if SOC_RW612
+
+config SOC_PART_NUMBER_RW612ETA1I
+	bool
+	select SOC_RW612
+
+config SOC_PART_NUMBER_RW612HNA1I
+	bool
+	select SOC_RW612
+
+config SOC_PART_NUMBER_RW612UKA1I
+	bool
+	select SOC_RW612
+
+config SOC_PART_NUMBER_RW610ETA1I
+	bool
+	select SOC_RW610
+
+config SOC_PART_NUMBER_RW610HNA1I
+	bool
+	select SOC_RW610
+
+config SOC_PART_NUMBER_RW610UKA1I
+	bool
+	select SOC_RW610
+
+config SOC_PART_NUMBER
+	string
+	default "RW612ETA1I" if SOC_PART_NUMBER_RW612ETA1I
+	default "RW612HNA1I" if SOC_PART_NUMBER_RW612HNA1I
+	default "RW612UKA1I" if SOC_PART_NUMBER_RW612UKA1I
+	default "RW610ETA1I" if SOC_PART_NUMBER_RW610ETA1I
+	default "RW610HNA1I" if SOC_PART_NUMBER_RW610HNA1I
+	default "RW610UKA1I" if SOC_PART_NUMBER_RW610UKA1I

soc/nxp/rw/boot_header.ld

@@ -0,0 +1,10 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+. = CONFIG_FLASH_CONFIG_OFFSET;
+KEEP(*(.flash_conf))
+. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
+KEEP(*(.boot_hdr.ivt))

soc/nxp/rw/flexspi_clock_setup.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright 2022-2023 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include "flexspi_clock_setup.h"
+#ifdef CONFIG_MEMC
+#include <fsl_flexspi.h>
+#include <fsl_clock.h>
+#endif
+
+/**
+ * @brief Set flexspi clock
+ */
+void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
+{
+	CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
+	CLKCTL0->FLEXSPIFCLKDIV |=
+		CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
+	CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
+	while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) {
+	}
+}

soc/nxp/rw/flexspi_clock_setup.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2022-2023 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _FLEXSPI_CLOCK_SETUP_H_
+#define _FLEXSPI_CLOCK_SETUP_H_
+
+#include "fsl_common.h"
+
+void set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider);
+
+#endif /* _FLEXSPI_CLOCK_SETUP_H_ */