everywhere: fix typos

Fix a lot of typos Signed-off-by: Nazar Kazakov <[email protected]>
tokangas · Mar 18, 2022 · f483b1b · f483b1b
1 parent 3b576fc
commit f483b1b
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diff --git a/.github/labeler.yml b/.github/labeler.yml
@@ -70,7 +70,7 @@
   - "arch/xtensa/**/*"
   - "include/arch/xtensa/**/*"
 "area: RISCV":
-  - "arch/risv/**/*"
+  - "arch/riscv/**/*"
   - "include/arch/riscv/**/*"
 "area: ARC":
   - "arch/arc/**/*"

diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -271,7 +271,7 @@ zephyr_compile_options(
 # ToDo: Remember to get feedback from Oticon on this, as they might use the `ASM_BASE_FLAG` since this is done this way.
 zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,required>>)
 
-# @Intent: Enforce standard integer type correspondance to match Zephyr usage.
+# @Intent: Enforce standard integer type correspondence to match Zephyr usage.
 # (must be after compiler specific flags)
 if(NOT CONFIG_ARCH_POSIX)
   # `zephyr_stdint.h` is not included for the POSIX (native) arch because it

diff --git a/arch/Kconfig b/arch/Kconfig
@@ -799,7 +799,7 @@ choice CACHE_TYPE
 config HAS_ARCH_CACHE
 	bool "Integrated cache controller"
 	help
-	  "Integrade on-core cache controller"
+	  "Integrated on-core cache controller"
 
 config HAS_EXTERNAL_CACHE
 	bool "External cache controller"

diff --git a/arch/arc/core/irq_manage.c b/arch/arc/core/irq_manage.c
@@ -135,7 +135,7 @@ void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 
 	__ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
 		 "invalid priority %d for irq %d", prio, irq);
-/* 0 -> CONFIG_NUM_IRQ_PRIO_LEVELS allocted to secure world
+/* 0 -> CONFIG_NUM_IRQ_PRIO_LEVELS allocated to secure world
  * left prio levels allocated to normal world
  */
 #if defined(CONFIG_ARC_SECURE_FIRMWARE)

diff --git a/arch/arm/core/aarch32/userspace.S b/arch/arm/core/aarch32/userspace.S
@@ -245,7 +245,7 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
     mov r0, lr
 
 #if defined(CONFIG_ARMV7_R)
-    /* change processor mode to unprivileged, with all interrrupts enabled. */
+    /* change processor mode to unprivileged, with all interrupts enabled. */
     msr CPSR_c, #MODE_USR
 #else
     /* change processor mode to unprivileged */

diff --git a/arch/posix/core/swap.c b/arch/posix/core/swap.c
@@ -23,7 +23,7 @@
 int arch_swap(unsigned int key)
 {
 	/*
-	 * struct k_thread * _current is the currently runnig thread
+	 * struct k_thread * _current is the currently running thread
 	 * struct k_thread * _kernel.ready_q.cache contains the next thread to
 	 * run (cannot be NULL)
 	 *

diff --git a/arch/riscv/core/pmp/core_pmp.c b/arch/riscv/core/pmp/core_pmp.c
@@ -271,7 +271,7 @@ static void csr_write_enum(int pmp_csr_enum, ulong_t value)
  *
  * Configure a memory region to be secured by one of the 16 PMP entries.
  *
- * @param index		Number of the targeted PMP entrie (0 to 15 only).
+ * @param index		Number of the targeted PMP entry (0 to 15 only).
  * @param cfg_val	Configuration value (cf datasheet or defined flags)
  * @param addr_val	Address register value
  *

diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c
@@ -55,7 +55,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	 * Following the RISC-V architecture,
 	 * the MSTATUS register (used to globally enable/disable interrupt),
 	 * as well as the MEPC register (used to by the core to save the
-	 * value of the program counter at which an interrupt/exception occcurs)
+	 * value of the program counter at which an interrupt/exception occurs)
 	 * need to be saved on the stack, upon an interrupt/exception
 	 * and restored prior to returning from the interrupt/exception.
 	 * This shall allow to handle nested interrupts.

diff --git a/arch/sparc/core/fatal.c b/arch/sparc/core/fatal.c
@@ -53,7 +53,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
  *
  * HOW TO USE
  *
- * When invesetigating a crashed program, the first things to look
+ * When investigating a crashed program, the first things to look
  * at is typically the tt, pc and sp (o6). You can lookup the pc
  * in the assembly list file or use addr2line. In the listing, the
  * register values in the table above can be used. The linker map
@@ -68,7 +68,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
  * g7 is the TLS pointer if enabled. A SAVE instruction decreases
  * the current window pointer (psr bits 4..0) which results in %o
  * registers becoming %i registers and a new set of %l registers
- * appear. RESTORE does the oppposite.
+ * appear. RESTORE does the opposite.
  */
 
 
@@ -85,7 +85,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
  *
  * When printing the registers, we get the "local" and "in"
  * registers from the ABI stack save area, while the "out" and
- * "global" registares are taken from the exception stack frame
+ * "global" registers are taken from the exception stack frame
  * generated in the fault trap entry.
  */
 struct savearea {

diff --git a/arch/x86/core/userspace.c b/arch/x86/core/userspace.c
@@ -23,7 +23,7 @@
  * we go through z_x86_trampoline_to_user.
  *
  * We don't need to update the privilege mode initial stack pointer either,
- * privilege elevation always lands on the trampoline stack and the irq/sycall
+ * privilege elevation always lands on the trampoline stack and the irq/syscall
  * code has to manually transition off of it to the appropriate stack after
  * switching page tables.
  */

diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c
@@ -977,7 +977,7 @@ static inline pentry_t pte_atomic_update(pentry_t *pte, pentry_t update_val,
  * bits and return the previous PTE value.
  *
  * Common mask values:
- *  MASK_ALL  - Update all PTE bits. Exitsing state totally discarded.
+ *  MASK_ALL  - Update all PTE bits. Existing state totally discarded.
  *  MASK_PERM - Only update permission bits. All other bits and physical
  *              mapping preserved.
  *
@@ -1147,7 +1147,7 @@ static int range_map_ptables(pentry_t *ptables, void *virt, uintptr_t phys,
  * @param size Size of the physical region to map
  * @param entry_flags Desired state of non-address PTE bits covered by mask,
  *                    ignored if OPTION_RESET
- * @param mask What bits in the PTE to actually modifiy; unset bits will
+ * @param mask What bits in the PTE to actually modify; unset bits will
  *             be preserved. Ignored if OPTION_RESET.
  * @param options Control options. Do not set OPTION_USER here. OPTION_FLUSH
  *                will trigger a TLB shootdown after all tables are updated.
@@ -1334,7 +1334,7 @@ static void identity_map_remove(uint32_t level)
 #endif
 
 /* Invoked to remove the identity mappings in the page tables,
- * they were only needed to tranisition the instruction pointer at early boot
+ * they were only needed to transition the instruction pointer at early boot
  */
 __boot_func
 void z_x86_mmu_init(void)

diff --git a/arch/xtensa/core/gdbstub.c b/arch/xtensa/core/gdbstub.c
@@ -981,7 +981,7 @@ void arch_gdb_init(void)
 	 * converting BREAK.N into BREAK which is bigger.
 	 * This is needed as the GDB stub will need to change
 	 * the program counter past this instruction to
-	 * continue working. Or else SoC would repeartedly
+	 * continue working. Or else SoC would repeatedly
 	 * raise debug exception on this instruction and
 	 * won't go forward.
 	 */

diff --git a/boards/arc/emsdp/support/openocd.cfg b/boards/arc/emsdp/support/openocd.cfg
@@ -7,7 +7,7 @@
 #
 
 # Configure JTAG cable
-# EM SDP has built-in FT2232 chip, which is similiar to Digilent HS-1.
+# EM SDP has built-in FT2232 chip, which is similar to Digilent HS-1.
 adapter driver ftdi
 
 # Only specify FTDI serial number if it is specified via

diff --git a/boards/arc/hsdk/support/openocd-2-cores.cfg b/boards/arc/hsdk/support/openocd-2-cores.cfg
@@ -4,7 +4,7 @@
 
 # Configure JTAG cable
 # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
-# it uses channgel B for JTAG, instead of channel A.
+# it uses channel B for JTAG, instead of channel A.
 adapter driver ftdi
 
 # Only specify FTDI serial number if it is specified via

diff --git a/boards/arc/hsdk/support/openocd.cfg b/boards/arc/hsdk/support/openocd.cfg
@@ -4,7 +4,7 @@
 
 # Configure JTAG cable
 # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
-# it uses channgel B for JTAG, instead of channel A.
+# it uses channel B for JTAG, instead of channel A.
 adapter driver ftdi
 
 # Only specify FTDI serial number if it is specified via

diff --git a/boards/arc/qemu_arc/doc/index.rst b/boards/arc/qemu_arc/doc/index.rst
@@ -80,7 +80,7 @@ QEMU, and display the following console output:
 
         *** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57  ***
         threadA: Hello World from qemu_arc!
-        threudB: Hello World from qemu_arc!
+        threadB: Hello World from qemu_arc!
         threadA: Hello World from qemu_arc!
         threadB: Hello World from qemu_arc!
 

diff --git a/boards/arm/96b_argonkey/doc/index.rst b/boards/arm/96b_argonkey/doc/index.rst
@@ -37,7 +37,7 @@ Hardware
   - Temperature/Pressure: STMicro LPS22HB
   - ALS: Intersil ISL29034
   - Proximity: STMicro VL53L0X
-  - Acclerometer/Gyroscope: STMicro LSM6DSL
+  - Accelerometer/Gyroscope: STMicro LSM6DSL
   - Geomagnetic: STMicro LIS2MDL
   - AMR Hall sensor: MRMS501A
   - Microphone: STMicro MP34DT05

diff --git a/boards/arm/96b_meerkat96/doc/index.rst b/boards/arm/96b_meerkat96/doc/index.rst
@@ -149,7 +149,7 @@ the remaining are not used/tested.
 Programming and Debugging
 *************************
 
-The 96Boards Meerakat96 board doesn't have QSPI flash for the M4 and it needs
+The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs
 to be started by the A7 core. The A7 core is responsible to load the M4 binary
 application into the RAM, put the M4 in reset, set the M4 Program Counter and
 Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at

diff --git a/boards/arm/96b_neonkey/doc/index.rst b/boards/arm/96b_neonkey/doc/index.rst
@@ -37,7 +37,7 @@ Hardware
   - Pressure: BMP280
   - ALS/Proximity: RPR-0521RS
   - Geomagnetic: BMM150
-  - Acclerometer/Gyroscope: BMI160
+  - Accelerometer/Gyroscope: BMI160
   - AMR Hall sensor: MRMS501A
   - Microphone: SPK0415HM4H-B
 

diff --git a/boards/arm/96b_stm32_sensor_mez/doc/index.rst b/boards/arm/96b_stm32_sensor_mez/doc/index.rst
@@ -32,7 +32,7 @@ Hardware
 - On board sensors:
 
   - Temperature/Pressure: STMicro LPS22HB
-  - Acclerometer/Gyroscope: STMicro LSM6DS3H
+  - Accelerometer/Gyroscope: STMicro LSM6DS3H
   - Magnetometer: STMicro LIS3MDL
   - Microphone: STMicro MP34DT01
 

diff --git a/boards/arm/arduino_nano_33_ble/doc/index.rst b/boards/arm/arduino_nano_33_ble/doc/index.rst
@@ -71,11 +71,11 @@ Connections and IOs
 The `schematic`_ will tell you everything
 you need to know about the pins.
 
-A convinience header mapping the Arduino pin names to their
+A convenience header mapping the Arduino pin names to their
 Zephyr pin numbers can be found in :code:`arduino_nano_33_ble_pins.h`,
 if you link against the :code:`arduino_nano_33_ble_pins` CMake library.
 
-For your convience, two Kconfig options are added:
+For your convenience, two Kconfig options are added:
 
 #. :code:`BOARD_ARDUINO_NANO_33_BLE_INIT_SENSORS`:
     This configuration option enables the internal I2C sensors.

diff --git a/boards/arm/arty/doc/index.rst b/boards/arm/arty/doc/index.rst
@@ -33,7 +33,7 @@ DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports
 both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
 targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3
 design only targets the Artix-7 based boards. Zephyr only supports the Artix-7
-targetted designs for now.
+targeted designs for now.
 
 For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
 following websites:

diff --git a/boards/arm/cc3220sf_launchxl/pinmux.c b/boards/arm/cc3220sf_launchxl/pinmux.c
@@ -78,7 +78,7 @@
  *  driverlib pin defines.  For example, I2C_CC32XX_PIN_01_I2C_SCL & 0xff = 0,
  *  which equals PIN_01 in driverlib pin.h.  By matching the PIN_xx defines in
  *  driverlib pin.h, we can pass the pin directly to the driverlib functions.
- *  The upper 8 bits of the macro correspond to the pin mux confg mode
+ *  The upper 8 bits of the macro correspond to the pin mux config mode
  *  value for the pin to operate in the I2C mode.  For example, pin 1 is
  *  configured with mode 1 to operate as I2C_SCL.
  */

diff --git a/boards/arm/cc3235sf_launchxl/pinmux.c b/boards/arm/cc3235sf_launchxl/pinmux.c
@@ -53,7 +53,7 @@
  *  driverlib pin defines.  For example, I2C_CC32XX_PIN_01_I2C_SCL & 0xff = 0,
  *  which equals PIN_01 in driverlib pin.h.  By matching the PIN_xx defines in
  *  driverlib pin.h, we can pass the pin directly to the driverlib functions.
- *  The upper 8 bits of the macro correspond to the pin mux confg mode
+ *  The upper 8 bits of the macro correspond to the pin mux config mode
  *  value for the pin to operate in the I2C mode.  For example, pin 1 is
  *  configured with mode 1 to operate as I2C_SCL.
  */

diff --git a/boards/arm/contextualelectronics_abc/doc/index.rst b/boards/arm/contextualelectronics_abc/doc/index.rst
@@ -1,12 +1,12 @@
 .. _contextualelectronics_abc:
 
-Contextual Eletronics Advanced BLE Cell
-#######################################
+Contextual Electronics Advanced BLE Cell
+########################################
 
 Overview
 ********
 
-The Contextual Eletronics ABC (PCA10056) hardware provides support for the
+The Contextual Electronics ABC (PCA10056) hardware provides support for the
 Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
 
 * CLOCK

diff --git a/boards/arm/cy8ckit_062_ble/doc/index.rst b/boards/arm/cy8ckit_062_ble/doc/index.rst
@@ -246,10 +246,10 @@ are only possible after rework the board and using the revision 1.0.0.
       :goals: build
       :compact:
 
-#. The diferences from version 0.0.0 to 1.0.0:
+#. The differences from version 0.0.0 to 1.0.0:
 
 +-------------+------------+------------+
-| Connecion   | 0.0.0      | 1.0.0      |
+| Connection  | 0.0.0      | 1.0.0      |
 +=============+============+============+
 | CDC-COM RX  | P5_0       | P9_0       |
 +-------------+------------+------------+

diff --git a/boards/arm/efm32wg_stk3800/doc/index.rst b/boards/arm/efm32wg_stk3800/doc/index.rst
@@ -41,7 +41,7 @@ For more information about the EFM32WG SoC and EFM32WG-STK3800 board:
 Supported Features
 ==================
 
-The efm32wg_stk3800oard configuration supports the following hardware features:
+The efm32wg_stk3800 board configuration supports the following hardware features:
 
 +-----------+------------+-------------------------------------+
 | Interface | Controller | Driver/Component                    |

diff --git a/boards/arm/frdm_k64f/doc/index.rst b/boards/arm/frdm_k64f/doc/index.rst
@@ -215,7 +215,7 @@ CAN
 ===
 
 The FRDM-K64F board does not come with an onboard CAN transceiver. In order to
-use the CAN bus, an external CAN bus tranceiver must be connected to ``PTB18``
+use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18``
 (``CAN0_TX``) and ``PTB19`` (``CAN0_RX``).
 
 Programming and Debugging

diff --git a/boards/arm/mec15xxevb_assy6853/doc/index.rst b/boards/arm/mec15xxevb_assy6853/doc/index.rst
@@ -9,7 +9,7 @@ Overview
 The MEC15xxEVB_ASSY6853 kit is a future development platform to evaluate the
 Microchip MEC15XX series microcontrollers. This board needs to be mated with
 part number MEC1501 144WFBA SOLDER DC ASSY 6860(cpu board) in order to operate.
-The MEC152x has superceded the MEC1501 in production. MEC152x is identical to
+The MEC152x has superseded the MEC1501 in production. MEC152x is identical to
 MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
 been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image
 formats are not compatible with each other. Evaluation and cpu boards are

diff --git a/boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst b/boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst
@@ -56,7 +56,7 @@ Other hardware features have not been enabled yet for this board.
 
 The default configuration can be found in the defconfig file:
 
-	``boards/arm/mikroe_clicker_2/mikroe_cliker_2_defconfig``
+	``boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig``
 
 Connections and IOs
 ===================

diff --git a/boards/arm/mm_feather/doc/index.rst b/boards/arm/mm_feather/doc/index.rst
@@ -198,7 +198,7 @@ Flashing
 
 Here is an example for the :ref:`hello_world` application.
 
-Connect a DAPLink debuger from your PC to corresponding SWD pins of SwiftIO Feather.
+Connect a DAPLink debugger from your PC to corresponding SWD pins of SwiftIO Feather.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world

diff --git a/boards/arm/nrf51_ble400/doc/index.rst b/boards/arm/nrf51_ble400/doc/index.rst
@@ -72,7 +72,7 @@ Motherboard
 3. I2C interface
 4. SPI interface
 5. 5V/3.3V power input/output: usually used as power output, also common-grounding with other user board
-6. USB connector: USB TO UART via onboard convertor CP2102
+6. USB connector: USB TO UART via onboard converter CP2102
 7. Debugging interface
 8. UART interface
 9. Battery holder

diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig b/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig
@@ -14,8 +14,8 @@ config BOARD
 # To let the nRF5 bootloader load an application, the application
 # must be linked after Nordic MBR, that is factory-programmed on the board.
 
-# Nordic nRF5 booatloader exists outside of the partitions specified in the
-# DTS file, so we manually override FLASH_LOAD_OFFEST to link the application
+# Nordic nRF5 bootloader exists outside of the partitions specified in the
+# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application
 # correctly, after Nordic MBR.
 
 # When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION

diff --git a/boards/arm/nucleo_g0b1re/doc/index.rst b/boards/arm/nucleo_g0b1re/doc/index.rst
@@ -63,7 +63,7 @@ Nucleo G0B1RE provides the following hardware components:
 - Tamper Pins(3)
 - 12-bit ADC with 16 channels
 - 12-bit DAC with 2 channels(2)
-- Analog Comperator(3)
+- Analog Comparator(3)
 - 12-channel DMA
 
 

diff --git a/boards/arm/nucleo_h723zg/support/openocd.cfg b/boards/arm/nucleo_h723zg/support/openocd.cfg
@@ -1,4 +1,4 @@
-# STM32H745ZI Nucleo board OpenOCD ST-LLINK V3 configuration
+# STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration
 #
 # Copyright (c) 2020 Alexander Kozhinov <[email protected]>
 # SPDX-License-Identifier: Apache-2.0
@@ -13,7 +13,7 @@ set BOARDNAME NUCLEO-H723ZG
 
 source [find target/stm32h7x.cfg]
 
-# Use connect_assert_srst here to be able to programm
+# Use connect_assert_srst here to be able to program
 # even when core is in sleep mode
 reset_config srst_only srst_nogate connect_assert_srst
 

diff --git a/boards/arm/nucleo_h745zi_q/support/openocd.cfg b/boards/arm/nucleo_h745zi_q/support/openocd.cfg
@@ -6,7 +6,7 @@
 
 source [find board/st_nucleo_h745zi.cfg]
 
-# Use connect_assert_srst here to be able to programm
+# Use connect_assert_srst here to be able to program
 # even when core is in sleep mode
 reset_config srst_only srst_nogate connect_assert_srst
 

diff --git a/boards/arm/nucleo_l152re/support/openocd.cfg b/boards/arm/nucleo_l152re/support/openocd.cfg
@@ -1,4 +1,4 @@
-# TODO: Once official oepnOCD fix merged and available in zephyr:
+# TODO: Once official openOCD fix merged and available in zephyr:
 #       http://openocd.zylin.com/#/c/5829/
 #       revert to board/st_nucleo_l1.cfg
 # source [find board/st_nucleo_l1.cfg]

diff --git a/boards/arm/olimex_stm32_h103/doc/index.rst b/boards/arm/olimex_stm32_h103/doc/index.rst
@@ -211,7 +211,7 @@ Programming and Debugging
 
 This board does not include any embedded debug tool interface, instead you
 will have to use an external probe connected to the available 20-pin JTAG
-connector to progran and debug the board. Both JTAG and SWD are supported.
+connector to program and debug the board. Both JTAG and SWD are supported.
 
 By default when using ``west debug`` ST-Link will be used with OpenOCD's
 SWD transport, but it is also possible to use JTAG with the Olimex ARM-USB-OCD-H