support comments in autogen files, so constant files are more friendly

bindings/const_generator.py

@@ -18,6 +18,8 @@
             'arm64.h': 'Arm64',
             'mips.h': 'Mips',
             'x86.h': 'X86',
+            'comment_open': '\t//',
+            'comment_close': '',
         },
     'python': {
             'header': "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n",
@@ -29,9 +31,14 @@
             'arm64.h': 'arm64',
             'mips.h': 'mips',
             'x86.h': 'x86',
+            'comment_open': '#',
+            'comment_close': '',
         }
 }
 
+# markup for comments to be added to autogen files
+MARKUP = '//>'
+
 def gen(templ):
     global include, INCL_DIR
     for target in include:
@@ -44,8 +51,15 @@ def gen(templ):
         count = 0
         for line in lines:
             line = line.strip()
+
+            if line.startswith(MARKUP):  # markup for comments
+                outfile.write("%s%s%s" %(templ['comment_open'], \
+                            line.replace(MARKUP, ''), templ['comment_close']))
+                continue
+
             if line == '' or line.startswith('//'):
                 continue
+
             if not line.startswith(prefix.upper()):
                 continue
 

bindings/java/capstone/Arm64_const.java

@@ -2,14 +2,14 @@
 package capstone;
 
 public class Arm64_const {
-
+	// ARM64 shift type
 	public static final int ARM64_SFT_INVALID = 0;
 	public static final int ARM64_SFT_LSL = 1;
 	public static final int ARM64_SFT_MSL = 2;
 	public static final int ARM64_SFT_LSR = 3;
 	public static final int ARM64_SFT_ASR = 4;
 	public static final int ARM64_SFT_ROR = 5;
-
+	// ARM64 extender type
 	public static final int ARM64_EXT_INVALID = 0;
 	public static final int ARM64_EXT_UXTB = 1;
 	public static final int ARM64_EXT_UXTH = 2;
@@ -19,7 +19,7 @@ public class Arm64_const {
 	public static final int ARM64_EXT_SXTH = 6;
 	public static final int ARM64_EXT_SXTW = 7;
 	public static final int ARM64_EXT_SXTX = 8;
-
+	// ARM64 condition code
 	public static final int ARM64_CC_INVALID = 0;
 	public static final int ARM64_CC_EQ = 1;
 	public static final int ARM64_CC_NE = 2;
@@ -37,14 +37,14 @@ public class Arm64_const {
 	public static final int ARM64_CC_LE = 14;
 	public static final int ARM64_CC_AL = 15;
 	public static final int ARM64_CC_NV = 16;
-
+	// Operand type for instruction's operands
 	public static final int ARM64_OP_INVALID = 0;
 	public static final int ARM64_OP_REG = 1;
 	public static final int ARM64_OP_CIMM = 2;
 	public static final int ARM64_OP_IMM = 3;
 	public static final int ARM64_OP_FP = 4;
 	public static final int ARM64_OP_MEM = 5;
-
+	// ARM64 registers
 	public static final int ARM64_REG_INVALID = 0;
 	public static final int ARM64_REG_NZCV = 1;
 	public static final int ARM64_REG_WSP = 2;
@@ -274,7 +274,7 @@ public class Arm64_const {
 	public static final int ARM64_REG_X29 = 226;
 	public static final int ARM64_REG_X30 = 227;
 	public static final int ARM64_REG_MAX = 228;
-
+	// ARM64 instruction
 	public static final int ARM64_INS_INVALID = 0;
 	public static final int ARM64_INS_ADC = 1;
 	public static final int ARM64_INS_ADDHN2 = 2;
@@ -642,7 +642,7 @@ public class Arm64_const {
 	public static final int ARM64_INS_NGC = 364;
 	public static final int ARM64_INS_NEG = 365;
 	public static final int ARM64_INS_MAX = 366;
-
+	// Group of ARM64 instructions
 	public static final int ARM64_GRP_INVALID = 0;
 	public static final int ARM64_GRP_NEON = 1;
 	public static final int ARM64_GRP_JUMP = 2;

bindings/java/capstone/Arm_const.java

@@ -2,7 +2,7 @@
 package capstone;
 
 public class Arm_const {
-
+	// ARM shift type
 	public static final int ARM_SFT_INVALID = 0;
 	public static final int ARM_SFT_ASR = 1;
 	public static final int ARM_SFT_LSL = 2;
@@ -14,7 +14,7 @@ public class Arm_const {
 	public static final int ARM_SFT_LSR_REG = 8;
 	public static final int ARM_SFT_ROR_REG = 9;
 	public static final int ARM_SFT_RRX_REG = 10;
-
+	// ARM condition code
 	public static final int ARM_CC_INVALID = 0;
 	public static final int ARM_CC_EQ = 1;
 	public static final int ARM_CC_NE = 2;
@@ -31,15 +31,15 @@ public class Arm_const {
 	public static final int ARM_CC_GT = 13;
 	public static final int ARM_CC_LE = 14;
 	public static final int ARM_CC_AL = 15;
-
+	// Operand type for instruction's operands
 	public static final int ARM_OP_INVALID = 0;
 	public static final int ARM_OP_REG = 1;
 	public static final int ARM_OP_CIMM = 2;
 	public static final int ARM_OP_PIMM = 3;
 	public static final int ARM_OP_IMM = 4;
 	public static final int ARM_OP_FP = 5;
 	public static final int ARM_OP_MEM = 6;
-
+	// ARM registers
 	public static final int ARM_REG_INVALID = 0;
 	public static final int ARM_REG_APSR = 1;
 	public static final int ARM_REG_APSR_NZCV = 2;
@@ -155,7 +155,7 @@ public class Arm_const {
 	public static final int ARM_REG_R13 = ARM_REG_SP;
 	public static final int ARM_REG_R14 = ARM_REG_LR;
 	public static final int ARM_REG_R15 = ARM_REG_PC;
-
+	// ARM instruction
 	public static final int ARM_INS_INVALID = 0;
 	public static final int ARM_INS_ADC = 1;
 	public static final int ARM_INS_ADD = 2;
@@ -579,7 +579,7 @@ public class Arm_const {
 	public static final int ARM_INS_POP = 420;
 	public static final int ARM_INS_PUSH = 421;
 	public static final int ARM_INS_MAX = 422;
-
+	// Group of ARM instructions
 	public static final int ARM_GRP_INVALID = 0;
 	public static final int ARM_GRP_CRYPTO = 1;
 	public static final int ARM_GRP_DATABARRIER = 2;

bindings/java/capstone/Mips_const.java

@@ -2,12 +2,12 @@
 package capstone;
 
 public class Mips_const {
-
+	// Operand type for instruction's operands
 	public static final int MIPS_OP_INVALID = 0;
 	public static final int MIPS_OP_REG = 1;
 	public static final int MIPS_OP_IMM = 2;
 	public static final int MIPS_OP_MEM = 3;
-
+	// MIPS registers
 	public static final int MIPS_REG_INVALID = 0;
 	public static final int MIPS_REG_0 = 1;
 	public static final int MIPS_REG_1 = 2;
@@ -170,7 +170,7 @@ public class Mips_const {
 	public static final int MIPS_REG_LO1 = MIPS_REG_HI1;
 	public static final int MIPS_REG_LO2 = MIPS_REG_HI2;
 	public static final int MIPS_REG_LO3 = MIPS_REG_HI3;
-
+	// MIPS instruction
 	public static final int MIPS_INS_INVALID = 0;
 	public static final int MIPS_INS_ABSQ_S = 1;
 	public static final int MIPS_INS_ADD = 2;
@@ -628,7 +628,7 @@ public class Mips_const {
 	public static final int MIPS_INS_XORI = 454;
 	public static final int MIPS_INS_NOP = 455;
 	public static final int MIPS_INS_MAX = 456;
-
+	// Group of MIPS instructions
 	public static final int MIPS_GRP_INVALID = 0;
 	public static final int MIPS_GRP_BITCOUNT = 1;
 	public static final int MIPS_GRP_DSP = 2;

bindings/java/capstone/X86_const.java

@@ -2,7 +2,7 @@
 package capstone;
 
 public class X86_const {
-
+	// X86 registers
 	public static final int X86_REG_INVALID = 0;
 	public static final int X86_REG_AH = 1;
 	public static final int X86_REG_AL = 2;
@@ -237,13 +237,13 @@ public class X86_const {
 	public static final int X86_REG_R14W = 231;
 	public static final int X86_REG_R15W = 232;
 	public static final int X86_REG_MAX = 233;
-
+	// Operand type for instruction's operands
 	public static final int X86_OP_INVALID = 0;
 	public static final int X86_OP_REG = 1;
 	public static final int X86_OP_IMM = 2;
 	public static final int X86_OP_FP = 3;
 	public static final int X86_OP_MEM = 4;
-
+	// X86 instructions
 	public static final int X86_INS_INVALID = 0;
 	public static final int X86_INS_AAA = 1;
 	public static final int X86_INS_AAD = 2;
@@ -1491,7 +1491,7 @@ public class X86_const {
 	public static final int X86_INS_XSTORE = 1244;
 	public static final int X86_INS_XTEST = 1245;
 	public static final int X86_INS_MAX = 1246;
-
+	// Group of X86 instructions
 	public static final int X86_GRP_INVALID = 0;
 	public static final int X86_GRP_3DNOW = 1;
 	public static final int X86_GRP_AES = 2;

bindings/python/capstone/arm64_const.py

@@ -1,12 +1,12 @@
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
-
+# ARM64 shift type
 ARM64_SFT_INVALID = 0
 ARM64_SFT_LSL = 1
 ARM64_SFT_MSL = 2
 ARM64_SFT_LSR = 3
 ARM64_SFT_ASR = 4
 ARM64_SFT_ROR = 5
-
+# ARM64 extender type
 ARM64_EXT_INVALID = 0
 ARM64_EXT_UXTB = 1
 ARM64_EXT_UXTH = 2
@@ -16,7 +16,7 @@
 ARM64_EXT_SXTH = 6
 ARM64_EXT_SXTW = 7
 ARM64_EXT_SXTX = 8
-
+# ARM64 condition code
 ARM64_CC_INVALID = 0
 ARM64_CC_EQ = 1
 ARM64_CC_NE = 2
@@ -34,14 +34,14 @@
 ARM64_CC_LE = 14
 ARM64_CC_AL = 15
 ARM64_CC_NV = 16
-
+# Operand type for instruction's operands
 ARM64_OP_INVALID = 0
 ARM64_OP_REG = 1
 ARM64_OP_CIMM = 2
 ARM64_OP_IMM = 3
 ARM64_OP_FP = 4
 ARM64_OP_MEM = 5
-
+# ARM64 registers
 ARM64_REG_INVALID = 0
 ARM64_REG_NZCV = 1
 ARM64_REG_WSP = 2
@@ -271,7 +271,7 @@
 ARM64_REG_X29 = 226
 ARM64_REG_X30 = 227
 ARM64_REG_MAX = 228
-
+# ARM64 instruction
 ARM64_INS_INVALID = 0
 ARM64_INS_ADC = 1
 ARM64_INS_ADDHN2 = 2
@@ -639,7 +639,7 @@
 ARM64_INS_NGC = 364
 ARM64_INS_NEG = 365
 ARM64_INS_MAX = 366
-
+# Group of ARM64 instructions
 ARM64_GRP_INVALID = 0
 ARM64_GRP_NEON = 1
 ARM64_GRP_JUMP = 2

bindings/python/capstone/arm_const.py

@@ -1,5 +1,5 @@
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
-
+# ARM shift type
 ARM_SFT_INVALID = 0
 ARM_SFT_ASR = 1
 ARM_SFT_LSL = 2
@@ -11,7 +11,7 @@
 ARM_SFT_LSR_REG = 8
 ARM_SFT_ROR_REG = 9
 ARM_SFT_RRX_REG = 10
-
+# ARM condition code
 ARM_CC_INVALID = 0
 ARM_CC_EQ = 1
 ARM_CC_NE = 2
@@ -28,15 +28,15 @@
 ARM_CC_GT = 13
 ARM_CC_LE = 14
 ARM_CC_AL = 15
-
+# Operand type for instruction's operands
 ARM_OP_INVALID = 0
 ARM_OP_REG = 1
 ARM_OP_CIMM = 2
 ARM_OP_PIMM = 3
 ARM_OP_IMM = 4
 ARM_OP_FP = 5
 ARM_OP_MEM = 6
-
+# ARM registers
 ARM_REG_INVALID = 0
 ARM_REG_APSR = 1
 ARM_REG_APSR_NZCV = 2
@@ -152,7 +152,7 @@
 ARM_REG_R13 = ARM_REG_SP
 ARM_REG_R14 = ARM_REG_LR
 ARM_REG_R15 = ARM_REG_PC
-
+# ARM instruction
 ARM_INS_INVALID = 0
 ARM_INS_ADC = 1
 ARM_INS_ADD = 2
@@ -576,7 +576,7 @@
 ARM_INS_POP = 420
 ARM_INS_PUSH = 421
 ARM_INS_MAX = 422
-
+# Group of ARM instructions
 ARM_GRP_INVALID = 0
 ARM_GRP_CRYPTO = 1
 ARM_GRP_DATABARRIER = 2

bindings/python/capstone/mips_const.py

@@ -1,10 +1,10 @@
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
-
+# Operand type for instruction's operands
 MIPS_OP_INVALID = 0
 MIPS_OP_REG = 1
 MIPS_OP_IMM = 2
 MIPS_OP_MEM = 3
-
+# MIPS registers
 MIPS_REG_INVALID = 0
 MIPS_REG_0 = 1
 MIPS_REG_1 = 2
@@ -167,7 +167,7 @@
 MIPS_REG_LO1 = MIPS_REG_HI1
 MIPS_REG_LO2 = MIPS_REG_HI2
 MIPS_REG_LO3 = MIPS_REG_HI3
-
+# MIPS instruction
 MIPS_INS_INVALID = 0
 MIPS_INS_ABSQ_S = 1
 MIPS_INS_ADD = 2
@@ -625,7 +625,7 @@
 MIPS_INS_XORI = 454
 MIPS_INS_NOP = 455
 MIPS_INS_MAX = 456
-
+# Group of MIPS instructions
 MIPS_GRP_INVALID = 0
 MIPS_GRP_BITCOUNT = 1
 MIPS_GRP_DSP = 2

bindings/python/capstone/x86_const.py

@@ -1,5 +1,5 @@
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
-
+# X86 registers
 X86_REG_INVALID = 0
 X86_REG_AH = 1
 X86_REG_AL = 2
@@ -234,13 +234,13 @@
 X86_REG_R14W = 231
 X86_REG_R15W = 232
 X86_REG_MAX = 233
-
+# Operand type for instruction's operands
 X86_OP_INVALID = 0
 X86_OP_REG = 1
 X86_OP_IMM = 2
 X86_OP_FP = 3
 X86_OP_MEM = 4
-
+# X86 instructions
 X86_INS_INVALID = 0
 X86_INS_AAA = 1
 X86_INS_AAD = 2
@@ -1488,7 +1488,7 @@
 X86_INS_XSTORE = 1244
 X86_INS_XTEST = 1245
 X86_INS_MAX = 1246
-
+# Group of X86 instructions
 X86_GRP_INVALID = 0
 X86_GRP_3DNOW = 1
 X86_GRP_AES = 2