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NiteFury-and-LiteFury Public
Forked from RHSResearchLLC/NiteFury-and-LiteFuryPublic repository for uEVB
SystemVerilog UpdatedJun 20, 2024 -
neoTRNG Public
Forked from stnolting/neoTRNG🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
VHDL BSD 3-Clause "New" or "Revised" License UpdatedJun 19, 2024 -
python-polar-coding Public
Forked from romaroman/python-polar-codingA model of Polar encoder/decoder
Python MIT License UpdatedJun 7, 2024 -
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pi-gen Public
Forked from RPi-Distro/pi-genTool used to create the official Raspberry Pi OS images
Shell BSD 3-Clause "New" or "Revised" License UpdatedJan 31, 2023 -
openssh-portable Public
Forked from openssh/openssh-portablePortable OpenSSH
C Other UpdatedAug 1, 2022 -
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infnoise Public
Forked from waywardgeek/infnoiseThe world's easiest TRNG to get right
C Creative Commons Zero v1.0 Universal UpdatedApr 30, 2022 -
hdl Public
Forked from analogdevicesinc/hdlHDL libraries and projects
Verilog Other UpdatedNov 10, 2021 -
migen Public
Forked from m-labs/migenA Python toolbox for building complex digital hardware
Python Other UpdatedSep 29, 2021 -
rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedSep 29, 2021 -
Practical-UVM-IEEE-Edition Public
Forked from Practical-UVM-Step-By-Step/Practical-UVM-IEEE-EditionThis is the repository for the IEEE version of the book
Verilog UpdatedSep 29, 2020 -
logic Public
Forked from tymonx/logicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
SystemVerilog Apache License 2.0 UpdatedJun 25, 2020 -
axi-in-chisel Public
Forked from maltanar/axi-in-chiselExamples for creating AXI-interfaced peripherals in Chisel
Scala MIT License UpdatedAug 19, 2016 -
redoubler Public
Forked from alwynallan/redoublerOpen RNG based on Modular Entropy Multiplication
Eagle GNU General Public License v3.0 UpdatedJun 2, 2016 -
uvm_axi_BFM-complex_transaction Public
Forked from funningboy/uvm_axiuvm AXI BFM(bus functional model)
Verilog UpdatedJun 23, 2013