slang-based frontend for Yosys

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Deep learning toolkit-enabled VLSI placement

This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024

Implementation of modified nodal analysis and model order reduction of RLC circuits

A complete open-source design-for-testing (DFT) Solution

An automatic clock gating utility

A modular build system for hardware

Verilog to Routing -- Open Source CAD Flow for FPGA Research

A Python platform for experiments with ABC, Yosys, and OpenSTA

Plugins developed for Yosys by the Open Road Project.

SERV - The SErial RISC-V CPU

This is the original 1978 BASIC Source code for the classic text-only Super Star Trek Game.

NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Mag…

LibreCores CI Github Action with FuseSoC driven flow

Julia wrapper for the Berkeley logic synthesis and verification program ABC

Delay Calculation ToolKit

The hackable text editor