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AVX-512: Removed "z" suffix from AVX-512 instructions, since it is in…
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…compatible with GCC.

I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
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Elena Demikhovsky committed Dec 11, 2013
1 parent e54c106 commit 3bf51cf
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Showing 11 changed files with 174 additions and 171 deletions.
198 changes: 100 additions & 98 deletions lib/Target/X86/X86InstrAVX512.td

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3 changes: 2 additions & 1 deletion lib/Target/X86/X86InstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -657,7 +657,8 @@ def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
def HasAVX : Predicate<"Subtarget->hasAVX()">;
def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
def HasAVX512 : Predicate<"Subtarget->hasAVX512()">;
def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
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8 changes: 4 additions & 4 deletions test/CodeGen/X86/avx512-arith.ll
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s

; CHECK-LABEL: addpd512
; CHECK: vaddpd
Expand Down Expand Up @@ -196,7 +196,7 @@ define <16 x i32> @vpmulld_test(<16 x i32> %i, <16 x i32> %j) {
}

; CHECK-LABEL: sqrtA
; CHECK: vsqrtssz
; CHECK: vsqrtss {{.*}} encoding: [0x62
; CHECK: ret
declare float @sqrtf(float) readnone
define float @sqrtA(float %a) nounwind uwtable readnone ssp {
Expand All @@ -206,7 +206,7 @@ entry:
}

; CHECK-LABEL: sqrtB
; CHECK: vsqrtsdz
; CHECK: vsqrtsd {{.*}}## encoding: [0x62
; CHECK: ret
declare double @sqrt(double) readnone
define double @sqrtB(double %a) nounwind uwtable readnone ssp {
Expand All @@ -216,7 +216,7 @@ entry:
}

; CHECK-LABEL: sqrtC
; CHECK: vsqrtssz
; CHECK: vsqrtss {{.*}}## encoding: [0x62
; CHECK: ret
declare float @llvm.sqrt.f32(float)
define float @sqrtC(float %a) nounwind {
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6 changes: 3 additions & 3 deletions test/CodeGen/X86/avx512-cmp.ll
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s

; CHECK: vucomisdz
; CHECK: vucomisd {{.*}}encoding: [0x62
define double @test1(double %a, double %b) nounwind {
%tobool = fcmp une double %a, %b
br i1 %tobool, label %l1, label %l2
Expand All @@ -13,7 +13,7 @@ l2:
ret double %c1
}

; CHECK: vucomissz
; CHECK: vucomiss {{.*}}encoding: [0x62
define float @test2(float %a, float %b) nounwind {
%tobool = fcmp olt float %a, %b
br i1 %tobool, label %l1, label %l2
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30 changes: 15 additions & 15 deletions test/CodeGen/X86/avx512-cvt.ll
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s

; CHECK-LABEL: sitof32
; CHECK: vcvtdq2ps %zmm
Expand Down Expand Up @@ -67,7 +67,7 @@ define <8 x double> @fpext00(<8 x float> %b) nounwind {
}

; CHECK-LABEL: funcA
; CHECK: vcvtsi2sdqz (%
; CHECK: vcvtsi2sdq (%rdi){{.*}} encoding: [0x62
; CHECK: ret
define double @funcA(i64* nocapture %e) {
entry:
Expand All @@ -77,7 +77,7 @@ entry:
}

; CHECK-LABEL: funcB
; CHECK: vcvtsi2sdlz (%
; CHECK: vcvtsi2sdl (%{{.*}} encoding: [0x62
; CHECK: ret
define double @funcB(i32* %e) {
entry:
Expand All @@ -87,7 +87,7 @@ entry:
}

; CHECK-LABEL: funcC
; CHECK: vcvtsi2sslz (%
; CHECK: vcvtsi2ssl (%{{.*}} encoding: [0x62
; CHECK: ret
define float @funcC(i32* %e) {
entry:
Expand All @@ -97,7 +97,7 @@ entry:
}

; CHECK-LABEL: i64tof32
; CHECK: vcvtsi2ssqz (%
; CHECK: vcvtsi2ssq (%{{.*}} encoding: [0x62
; CHECK: ret
define float @i64tof32(i64* %e) {
entry:
Expand All @@ -107,7 +107,7 @@ entry:
}

; CHECK-LABEL: fpext
; CHECK: vcvtss2sdz
; CHECK: vcvtss2sd {{.*}} encoding: [0x62
; CHECK: ret
define void @fpext() {
entry:
Expand All @@ -120,9 +120,9 @@ entry:
}

; CHECK-LABEL: fpround_scalar
; CHECK: vmovsdz
; CHECK: vcvtsd2ssz
; CHECK: vmovssz
; CHECK: vmovsd {{.*}} encoding: [0x62
; CHECK: vcvtsd2ss {{.*}} encoding: [0x62
; CHECK: vmovss {{.*}} encoding: [0x62
; CHECK: ret
define void @fpround_scalar() nounwind uwtable {
entry:
Expand All @@ -135,31 +135,31 @@ entry:
}

; CHECK-LABEL: long_to_double
; CHECK: vmovqz
; CHECK: vmovq {{.*}} encoding: [0x62
; CHECK: ret
define double @long_to_double(i64 %x) {
%res = bitcast i64 %x to double
ret double %res
}

; CHECK-LABEL: double_to_long
; CHECK: vmovqz
; CHECK: vmovq {{.*}} encoding: [0x62
; CHECK: ret
define i64 @double_to_long(double %x) {
%res = bitcast double %x to i64
ret i64 %res
}

; CHECK-LABEL: int_to_float
; CHECK: vmovdz
; CHECK: vmovd {{.*}} encoding: [0x62
; CHECK: ret
define float @int_to_float(i32 %x) {
%res = bitcast i32 %x to float
ret float %res
}

; CHECK-LABEL: float_to_int
; CHECK: vmovdz
; CHECK: vmovd {{.*}} encoding: [0x62
; CHECK: ret
define i32 @float_to_int(float %x) {
%res = bitcast float %x to i32
Expand All @@ -185,15 +185,15 @@ define <16 x float> @uitof32(<16 x i32> %a) nounwind {
}

; CHECK-LABEL: @fptosi02
; CHECK vcvttss2siz
; CHECK vcvttss2si {{.*}} encoding: [0x62
; CHECK: ret
define i32 @fptosi02(float %a) nounwind {
%b = fptosi float %a to i32
ret i32 %b
}

; CHECK-LABEL: @fptoui02
; CHECK vcvttss2usiz
; CHECK vcvttss2usi {{.*}} encoding: [0x62
; CHECK: ret
define i32 @fptoui02(float %a) nounwind {
%b = fptoui float %a to i32
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10 changes: 5 additions & 5 deletions test/CodeGen/X86/avx512-insert-extract.ll
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ define <8 x i64> @test4(<8 x i64> %x) nounwind {
}

;CHECK-LABEL: test5:
;CHECK: vextractpsz
;CHECK: vextractps
;CHECK: ret
define i32 @test5(<4 x float> %x) nounwind {
%ef = extractelement <4 x float> %x, i32 3
Expand All @@ -53,7 +53,7 @@ define i32 @test5(<4 x float> %x) nounwind {
}

;CHECK-LABEL: test6:
;CHECK: vextractpsz {{.*}}, (%rdi)
;CHECK: vextractps {{.*}}, (%rdi)
;CHECK: ret
define void @test6(<4 x float> %x, float* %out) nounwind {
%ef = extractelement <4 x float> %x, i32 3
Expand All @@ -62,7 +62,7 @@ define void @test6(<4 x float> %x, float* %out) nounwind {
}

;CHECK-LABEL: test7
;CHECK: vmovdz
;CHECK: vmovd
;CHECK: vpermps %zmm
;CHECK: ret
define float @test7(<16 x float> %x, i32 %ind) nounwind {
Expand All @@ -71,7 +71,7 @@ define float @test7(<16 x float> %x, i32 %ind) nounwind {
}

;CHECK-LABEL: test8
;CHECK: vmovqz
;CHECK: vmovq
;CHECK: vpermpd %zmm
;CHECK: ret
define double @test8(<8 x double> %x, i32 %ind) nounwind {
Expand All @@ -89,7 +89,7 @@ define float @test9(<8 x float> %x, i32 %ind) nounwind {
}

;CHECK-LABEL: test10
;CHECK: vmovdz
;CHECK: vmovd
;CHECK: vpermd %zmm
;CHEKK: vmovdz %xmm0, %eax
;CHECK: ret
Expand Down
22 changes: 11 additions & 11 deletions test/CodeGen/X86/avx512-intrinsics.ll
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s

declare i32 @llvm.x86.avx512.kortestz.w(i16, i16) nounwind readnone
; CHECK-LABEL: test_kortestz
Expand Down Expand Up @@ -147,73 +147,73 @@ define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) {
declare <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float>) nounwind readnone

define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vsqrtssz
; CHECK: vsqrtss {{.*}}encoding: [0x62
%res = call <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
declare <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float>, <4 x float>) nounwind readnone

define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vsqrtsdz
; CHECK: vsqrtsd {{.*}}encoding: [0x62
%res = call <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double>, <2 x double>) nounwind readnone

define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
; CHECK: vcvtsd2siz
; CHECK: vcvtsd2si {{.*}}encoding: [0x62
%res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone

define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
; CHECK: vcvtsi2sdqz
; CHECK: vcvtsi2sdq {{.*}}encoding: [0x62
%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone

define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) {
; CHECK: vcvtusi2sdqz
; CHECK: vcvtusi2sdq {{.*}}encoding: [0x62
%res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
ret <2 x double> %res
}
declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone

define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
; CHECK: vcvttsd2siz
; CHECK: vcvttsd2si {{.*}}encoding: [0x62
%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone


define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) {
; CHECK: vcvtss2siz
; CHECK: vcvtss2si {{.*}}encoding: [0x62
%res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone


define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
; CHECK: vcvtsi2ssqz
; CHECK: vcvtsi2ssq {{.*}}encoding: [0x62
%res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
ret <4 x float> %res
}
declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone


define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
; CHECK: vcvttss2siz
; CHECK: vcvttss2si {{.*}}encoding: [0x62
%res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1]
ret i64 %res
}
declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone

define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
; CHECK: vcvtsd2usiz
; CHECK: vcvtsd2usi {{.*}}encoding: [0x62
%res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
Expand Down
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