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Remove the caching of the target machine from SystemZTargetLowering.
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Update all callers and uses accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211880 91177308-0d34-0410-b5e6-96231b3b80d8
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@echristo
echristo committed Jun 27, 2014
1 parent d023a35 commit 4299a8b
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Showing 2 changed files with 33 additions and 21 deletions.
53 changes: 33 additions & 20 deletions lib/Target/SystemZ/SystemZISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {

SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
: TargetLowering(tm, new TargetLoweringObjectFileELF()),
Subtarget(*tm.getSubtargetImpl()), TM(tm) {
Subtarget(*tm.getSubtargetImpl()) {
MVT PtrVT = getPointerTy();

// Set up the register classes.
Expand Down Expand Up @@ -673,11 +673,13 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
MachineRegisterInfo &MRI = MF.getRegInfo();
SystemZMachineFunctionInfo *FuncInfo =
MF.getInfo<SystemZMachineFunctionInfo>();
auto *TFL = static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
auto *TFL = static_cast<const SystemZFrameLowering *>(
DAG.getTarget().getFrameLowering());

// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
CCState CCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
*DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);

unsigned NumFixedGPRs = 0;
Expand Down Expand Up @@ -815,7 +817,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,

// Analyze the operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
CCState ArgCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
*DAG.getContext());
ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);

// We don't support GuaranteedTailCallOpt, only automatically-detected
Expand Down Expand Up @@ -931,7 +934,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,

// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
*DAG.getContext());
RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);

// Copy all of the result registers out of their specified physreg.
Expand Down Expand Up @@ -962,7 +966,8 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,

// Assign locations to each returned value.
SmallVector<CCValAssign, 16> RetLocs;
CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
*DAG.getContext());
RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);

// Quick exit for void returns
Expand Down Expand Up @@ -1786,8 +1791,8 @@ SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
const GlobalValue *GV = Node->getGlobal();
int64_t Offset = Node->getOffset();
EVT PtrVT = getPointerTy();
Reloc::Model RM = TM.getRelocationModel();
CodeModel::Model CM = TM.getCodeModel();
Reloc::Model RM = DAG.getTarget().getRelocationModel();
CodeModel::Model CM = DAG.getTarget().getCodeModel();

SDValue Result;
if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
Expand Down Expand Up @@ -1824,7 +1829,7 @@ SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
SDLoc DL(Node);
const GlobalValue *GV = Node->getGlobal();
EVT PtrVT = getPointerTy();
TLSModel::Model model = TM.getTLSModel(GV);
TLSModel::Model model = DAG.getTarget().getTLSModel(GV);

if (model != TLSModel::LocalExec)
llvm_unreachable("only local-exec TLS mode supported");
Expand Down Expand Up @@ -2287,9 +2292,9 @@ SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
// Use an addition if the operand is constant and either LAA(G) is
// available or the negative value is in the range of A(G)FHI.
int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
if (isInt<32>(Value) || TM.getSubtargetImpl()->hasInterlockedAccess1())
if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
NegSrc2 = DAG.getConstant(Value, MemVT);
} else if (TM.getSubtargetImpl()->hasInterlockedAccess1())
} else if (Subtarget.hasInterlockedAccess1())
// Use LAA(G) if available.
NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
Src2);
Expand Down Expand Up @@ -2602,7 +2607,8 @@ static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
MachineBasicBlock *
SystemZTargetLowering::emitSelect(MachineInstr *MI,
MachineBasicBlock *MBB) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
MBB->getParent()->getTarget().getInstrInfo());

unsigned DestReg = MI->getOperand(0).getReg();
unsigned TrueReg = MI->getOperand(1).getReg();
Expand Down Expand Up @@ -2650,7 +2656,8 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI,
MachineBasicBlock *MBB,
unsigned StoreOpcode, unsigned STOCOpcode,
bool Invert) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
MBB->getParent()->getTarget().getInstrInfo());

unsigned SrcReg = MI->getOperand(0).getReg();
MachineOperand Base = MI->getOperand(1);
Expand All @@ -2665,7 +2672,7 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI,
// Use STOCOpcode if possible. We could use different store patterns in
// order to avoid matching the index register, but the performance trade-offs
// might be more complicated in that case.
if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
if (Invert)
CCMask ^= CCValid;
BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
Expand Down Expand Up @@ -2717,8 +2724,9 @@ SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
unsigned BinOpcode,
unsigned BitSize,
bool Invert) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
bool IsSubWord = (BitSize < 32);

Expand Down Expand Up @@ -2840,8 +2848,9 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
unsigned CompareOpcode,
unsigned KeepOldMask,
unsigned BitSize) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
bool IsSubWord = (BitSize < 32);

Expand Down Expand Up @@ -2951,8 +2960,9 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
MachineBasicBlock *
SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
MachineBasicBlock *MBB) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();

// Extract the operands. Base can be a register or a frame index.
Expand Down Expand Up @@ -3067,8 +3077,9 @@ MachineBasicBlock *
SystemZTargetLowering::emitExt128(MachineInstr *MI,
MachineBasicBlock *MBB,
bool ClearEven, unsigned SubReg) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI->getDebugLoc();

Expand Down Expand Up @@ -3098,8 +3109,9 @@ MachineBasicBlock *
SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
MachineBasicBlock *MBB,
unsigned Opcode) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI->getDebugLoc();

Expand Down Expand Up @@ -3267,8 +3279,9 @@ MachineBasicBlock *
SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
MachineBasicBlock *MBB,
unsigned Opcode) const {
const SystemZInstrInfo *TII = TM.getInstrInfo();
MachineFunction &MF = *MBB->getParent();
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
MachineRegisterInfo &MRI = MF.getRegInfo();
DebugLoc DL = MI->getDebugLoc();

Expand Down
1 change: 0 additions & 1 deletion lib/Target/SystemZ/SystemZISelLowering.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -249,7 +249,6 @@ class SystemZTargetLowering : public TargetLowering {

private:
const SystemZSubtarget &Subtarget;
const SystemZTargetMachine &TM;

// Implement LowerOperation for individual opcodes.
SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
Expand Down

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